vhdl
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：6KB
下载次数：46
上传日期：2010-06-27 14:48:11
上 传 者：
mq334
说明： 该系统通过顶层模块，调用7底层模块实现。7大模块底层模块为：理想信源数据接收模块，理想信源数据缓存模块，LAPS成帧模块，加扰并发送LAPS帧模块，接收LAPS帧并解扰模块，接收LAPS帧数据缓存模块，解帧并发送数据给理想信源模块。另，还有一个fifo模块，以便两个缓存模块调用。
(The system top-level module, called 7, the bottom module. Bottom-7 module module: the ideal source of data receiver module, an ideal source of data cache module, LAPS framing module, scrambling and send LAPS frame module, receiving and descrambling module LAPS frame, receive LAPS frame data buffer module, solution frame and sending data to a good source module. The other, there is a fifo module to call the two cache modules.)
文件列表:
vhdl\data_receive.vhd (3268, 2009-11-15)
vhdl\deframe.vhd (5880, 2009-11-15)
vhdl\enframe.vhd (2062, 2009-11-15)
vhdl\fifo.vhd (4374, 2009-11-15)
vhdl\main.vhd (5233, 2009-11-15)
vhdl\rxfifo.vhd (1138, 2009-11-15)
vhdl\scram_dncode.vhd (1504, 2009-11-15)
vhdl\scram_encode.vhd (1454, 2009-11-15)
vhdl\txfifo.vhd (1109, 2009-11-15)
vhdl (0, 2009-11-15)
main.vhd ---顶层模块
data_receive.vhd ---理想信源数据接收模块
rxfifo.vhd ---理想信源数据缓存模块
enframe.vhd ---LAPS成帧模块
scram_encode ---加扰模块
scram_dncode ---解扰模块
txfifo.vhd ---接收LAPS帧数据缓存模块
deframe.vhd ---解帧并发送数据给理想信源模块
fifo.vhd ---FIFO模块
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