mem_ctrl
所属分类：VHDL/FPGA/Verilog
开发工具：Windows_Unix
文件大小：388KB
下载次数：51
上传日期：2010-06-28 14:27:52
上 传 者：
Fei_Fly
说明： 老外写的通用的存储器控制核，支持SDRAM SSRAM FLASH,ROM等等 8个片选信号 支持RMW cycles最大可达9*64M Bytes的存储器容量
(Written by foreigners universal memory controller core, support for SDRAM SSRAM FLASH, ROM, etc. 8 chip select signals support RMW cycles up to 9* 64M Bytes of memory capacity)
文件列表:
mem_ctrl\bench\CVS\Entries (39, 2008-08-28)
mem_ctrl\bench\CVS\Repository (15, 2008-08-28)
mem_ctrl\bench\CVS\Root (13, 2008-08-28)
mem_ctrl\bench\CVS (0, 2008-08-29)
mem_ctrl\bench\richard\CVS\Entries (14, 2008-08-28)
mem_ctrl\bench\richard\CVS\Repository (23, 2008-08-28)
mem_ctrl\bench\richard\CVS\Root (13, 2008-08-28)
mem_ctrl\bench\richard\CVS (0, 2008-08-29)
mem_ctrl\bench\richard\verilog\bench.v (12649, 2002-03-06)
mem_ctrl\bench\richard\verilog\checkers.v (5914, 2002-03-06)
mem_ctrl\bench\richard\verilog\CVS\Entries (415, 2008-08-28)
mem_ctrl\bench\richard\verilog\CVS\Repository (31, 2008-08-28)
mem_ctrl\bench\richard\verilog\CVS\Root (13, 2008-08-28)
mem_ctrl\bench\richard\verilog\CVS (0, 2008-08-29)
mem_ctrl\bench\richard\verilog\mc_defines.v (8312, 2002-03-06)
mem_ctrl\bench\richard\verilog\models\CVS\Entries (136, 2008-08-28)
mem_ctrl\bench\richard\verilog\models\CVS\Repository (38, 2008-08-28)
mem_ctrl\bench\richard\verilog\models\CVS\Root (13, 2008-08-28)
mem_ctrl\bench\richard\verilog\models\CVS (0, 2008-08-29)
mem_ctrl\bench\richard\verilog\models\m8kx8.v (7052, 2002-03-06)
mem_ctrl\bench\richard\verilog\models\mt48lc16m16a2.v (48522, 2002-03-06)
mem_ctrl\bench\richard\verilog\models\mt58l1my18d.v (9360, 2002-03-06)
mem_ctrl\bench\richard\verilog\models (0, 2008-08-29)
mem_ctrl\bench\richard\verilog\timescale.v (23, 2002-03-06)
mem_ctrl\bench\richard\verilog\tst_asram.v (8843, 2002-03-06)
mem_ctrl\bench\richard\verilog\tst_multi_mem.v (18871, 2002-03-06)
mem_ctrl\bench\richard\verilog\tst_sdram.v (45455, 2002-03-06)
mem_ctrl\bench\richard\verilog\tst_ssram.v (6331, 2002-03-06)
mem_ctrl\bench\richard\verilog\wb_master_model.v (9469, 2002-03-06)
mem_ctrl\bench\richard\verilog (0, 2008-08-29)
mem_ctrl\bench\richard (0, 2008-08-29)
mem_ctrl\bench\verilog\160b3ver\adv_bb.v (40044, 2001-11-29)
mem_ctrl\bench\verilog\160b3ver\CVS\Entries (563, 2008-08-28)
mem_ctrl\bench\verilog\160b3ver\CVS\Repository (32, 2008-08-28)
mem_ctrl\bench\verilog\160b3ver\CVS\Root (13, 2008-08-28)
mem_ctrl\bench\verilog\160b3ver\CVS (0, 2008-08-29)
mem_ctrl\bench\verilog\160b3ver\dp160b3b.v (8778, 2001-07-29)
mem_ctrl\bench\verilog\160b3ver\DP160B3B_RU.V (3733, 2001-07-29)
mem_ctrl\bench\verilog\160b3ver\dp160b3t.v (8775, 2001-07-29)
mem_ctrl\bench\verilog\160b3ver\f160b3b.bkb (5672, 2001-07-29)
... ...
The WISHBONE Advanced Memory Controller
http://www.opencores.org/cores/mem_ctrl
To find out more about me (Rudolf Usselmann), please visit:
http://www.asics.ws
Directory Structure
-------------------
[core_root]
|
+-doc Documentation
|
+-bench--+ Test Bench
| +- verilog Verilog Sources
| +-vhdl VHDL Sources
|
+-rtl----+ Core RTL Sources
| +-verilog Verilog Sources
| +-vhdl VHDL Sources
|
+-sim----+
| +-rtl_sim---+ Functional verification Directory
| | +-bin Makefiles/Run Scripts
| | +-run Working Directory
| |
| +-gate_sim--+ Functional & Timing Gate Level
| | Verification Directory
| +-bin Makefiles/Run Scripts
| +-run Working Directory
|
+-lint--+ Lint Directory Tree
| +-bin Makefiles/Run Scripts
| +-run Working Directory
| +-log Linter log & result files
|
+-syn---+ Synthesis Directory Tree
| +-bin Synthesis Scripts
| +-run Working Directory
| +-log Synthesis log files
| +-out Synthesis Output
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