说明：  VHDL四路抢答器该任务分成七个模块进行设计，分别为：抢答器鉴别模块、抢答器计时模块、抢答器记分模块、分频模块、译码模块、数选模块、报警模块，最后是撰写顶层文件。
(VHDL four Responder divided into seven modules of the design task, namely: Responder identification module, timing module Responder, Responder scoring module, frequency module, decoding module, the number of selected modules, alarm modules, and finally writing top-level document.)