fpgacis
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：1072KB
下载次数：117
上传日期：2010-07-06 12:11:01
上 传 者：
岚风秋叶
说明： 主要是通过使用FPGA利用CIS（接触式图像传感器）进行图像采集，通过AD转换之后把数据存储到FPGA里面开辟的FIFO
(Mainly through the use of FPGA utilization of CIS (non-contact image sensor) image acquisition, through the data storage after AD transform to open the FIFO FPGA inside)
文件列表:
FPGA_cis control\AD.lfp (1066, 2007-08-10)
FPGA_cis control\AD.ucf (2077, 2007-10-06)
FPGA_cis control\ADControl.ise (5491, 2009-09-15)
FPGA_cis control\ADControl.ise_ISE_Backup (5491, 2009-09-15)
FPGA_cis control\ADControl.mcs (368356, 2007-08-11)
FPGA_cis control\ADControl.prm (656, 2007-08-11)
FPGA_cis control\ADControl.sig (239, 2007-08-11)
FPGA_cis control\automake.log (0, 2009-09-15)
FPGA_cis control\bbs_lock (48, 2007-08-13)
FPGA_cis control\core.tpl (3546, 2007-10-25)
FPGA_cis control\ADControl.dhp (9468, 2009-09-15)
FPGA_cis control\dcm1_arwz.xaw (3143, 2007-08-04)
FPGA_cis control\dcm1_arwz_arwz.ucf (686, 2007-08-04)
FPGA_cis control\dcm2_arwz.xaw (3671, 2007-08-04)
FPGA_cis control\dcm2_arwz_arwz.ucf (684, 2007-08-04)
FPGA_cis control\dcm3_arwz.xaw (3294, 2007-08-04)
FPGA_cis control\dcm3_arwz_arwz.ucf (686, 2007-08-04)
FPGA_cis control\dds_ip.asy (464, 2007-10-25)
FPGA_cis control\dds_ip.edn (126227, 2007-10-25)
FPGA_cis control\dds_ip.ngo (56508, 2007-10-26)
FPGA_cis control\dds_ip.sym (722, 2007-10-25)
FPGA_cis control\dds_ip.v (42114, 2007-10-25)
FPGA_cis control\dds_ip.veo (2971, 2007-10-25)
FPGA_cis control\dds_ip.vhd (39703, 2007-10-25)
FPGA_cis control\dds_ip.vho (3556, 2007-10-25)
FPGA_cis control\dds_ip.xco (1385, 2007-10-25)
FPGA_cis control\dds_ip_flist.txt (183, 2007-10-25)
FPGA_cis control\dds_ip_SINCOS_TABLE_TRIG_ROM.mif (14336, 2007-10-25)
FPGA_cis control\fifo_ip.asy (1017, 2007-08-13)
FPGA_cis control\fifo_ip.edn (15440, 2007-08-13)
FPGA_cis control\fifo_ip.ngo (15212, 2007-08-13)
FPGA_cis control\fifo_ip.sym (1580, 2007-08-13)
FPGA_cis control\fifo_ip.v (5384, 2007-08-13)
FPGA_cis control\fifo_ip.veo (3096, 2007-08-13)
FPGA_cis control\fifo_ip.vhd (5365, 2007-08-13)
FPGA_cis control\fifo_ip.vho (3871, 2007-08-13)
FPGA_cis control\fifo_ip.xco (1870, 2007-08-13)
FPGA_cis control\fifo_ip_fifo_generator_v2_0_as_1.ngc (145560, 2007-08-13)
FPGA_cis control\fifo_ip_fifo_generator_v2_0_ss_1.ngc (120048, 2007-08-13)
... ...
The following files were generated for in directory
F:\CG\AD\Programs\ADControl_v1_3\FPGA_VHDL:
dds_ip.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
dds_ip.edn:
Electronic Data Netlist (EDN) file containing the information
required to implement the module in a Xilinx (R) FPGA.
dds_ip.sym:
Please see the core data sheet.
dds_ip.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
dds_ip.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
dds_ip.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
dds_ip.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
dds_ip.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
dds_ip_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
dds_ip_readme.txt:
Text file indicating the files generated and how they are used.
dds_ip_SINCOS_TABLE_TRIG_ROM.mif:
Memory Initialization File which is automatically generated by the
CORE Generator System for some modules when a simulation flow is
specified. A MIF data file is used to support HDL functional
simulation of modules which use arrays of values.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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