ref-sdr-sdram-verilog

所属分类:VHDL/FPGA/Verilog
开发工具:MultiPlatform
文件大小:758KB
下载次数:428
上传日期:2005-11-14 10:50:22
上 传 者wangxu0012003
说明:  本代码是用VRILOG语言写的SDRAM的控制器的标准代码,供开发SARM参考.
(this code is used to write the language VRILOG SDRAM controller standard code for the development of SARM reference.)

文件列表:
doc (0, 2002-09-11)
sdr_sdram.pdf (917283, 2002-09-02)
simulation (0, 2002-09-11)
simulation\sdr_sdram_tb.v (22444, 2000-07-12)
source (0, 2002-09-11)
source\altclklock.v (8543, 2000-06-12)
source\Command.v (17328, 2000-07-28)
source\compile_all.v (206, 2000-05-19)
source\control_interface.v (8463, 2000-07-28)
source\Params.v (935, 2000-07-06)
source\PLL1.v (4754, 2000-05-23)
source\sdr_data_path.v (2747, 2000-07-28)
source\sdr_sdram.v (6942, 2000-07-28)

SDR SDRAM Controller v1.1 readme.txt This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1. The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen architecture. Last updated September, 2002 Copyright 2002 Altera Corporation. All rights reserved.

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