add_full_n
所属分类：VHDL/FPGA/Verilog
开发工具：Unix_Linux
文件大小：21KB
下载次数：19
上传日期：2005-11-15 16:32:54
上 传 者：
xujia751
说明： 该程序实现的是n位全加器，首先用与非门实现一位全家器，最后实现n位的全加器。
(the program is to achieve the n-bit full adder, first using the door with non-realization of a family- and finally realize the full n-bit adder.)
文件列表:
add_full_n (0, 2005-11-01)
add_full_n\add_full.vhd (697, 2005-11-01)
add_full_n\add_full_n.prd (280, 2005-11-01)
add_full_n\add_full_n.prj (1294, 2005-11-01)
add_full_n\add_full_n.vhd (922, 2005-11-01)
add_full_n\flatsch.sxr (58, 2005-11-01)
add_full_n\not_and.vhd (249, 2005-11-01)
add_full_n\rev_1 (0, 2005-11-01)
add_full_n\rev_1\.recordref (0, 2005-11-01)
add_full_n\rev_1\not_and.areasrr (681, 2005-11-01)
add_full_n\rev_1\not_and.edn (16212, 2005-11-01)
add_full_n\rev_1\not_and.fse (0, 2005-11-01)
add_full_n\rev_1\not_and.htm (332, 2005-11-01)
add_full_n\rev_1\not_and.sdf (355, 2005-11-01)
add_full_n\rev_1\not_and.srd (6884, 2005-11-01)
add_full_n\rev_1\not_and.srm (9692, 2005-11-01)
add_full_n\rev_1\not_and.srr (7698, 2005-11-01)
add_full_n\rev_1\not_and.srs (4728, 2005-11-01)
add_full_n\rev_1\not_and.tlg (634, 2005-11-01)
add_full_n\rev_1\not_and_sdc.sdc (310, 2005-11-01)
add_full_n\rev_1\syntmp (0, 2005-11-01)
add_full_n\rev_1\syntmp\add_full_n_flink.htm (350, 2005-11-01)
add_full_n\rev_1\syntmp\not_and.plg (280, 2005-11-01)
add_full_n\rev_1\syntmp\not_and_flink.htm (350, 2005-11-01)
add_full_n\rev_1\syntmp\not_and_srr.htm (8928, 2005-11-01)
add_full_n\rev_1\syntmp\not_and_toc.htm (1069, 2005-11-01)
add_full_n\rev_1\syntmp\tb_add_full_n.msg (0, 2005-11-01)
add_full_n\rev_1\syntmp\tb_add_full_n_flink.htm (350, 2005-11-01)
add_full_n\rev_1\syntmp\tb_add_full_n_srr.htm (962, 2005-11-01)
add_full_n\rev_1\syntmp\tb_add_full_n_toc.htm (455, 2005-11-01)
add_full_n\rev_1\tb_add_full_n.htm (356, 2005-11-01)
add_full_n\rev_1\tb_add_full_n.srr (620, 2005-11-01)
add_full_n\tb_add_full_n.vhd (682, 2005-11-01)
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