文件列表:

CDMA2000\CDMA2000_DDC_S3\seq_adder.m (69, 2004-10-05)
CDMA2000\CDMA2000_DDC_S3\cdma2000_DDC_4_channel_s3.mdl (1482622, 2005-02-03)
CDMA2000\CDMA2000_DDC_S3\getDATableValues.m (464, 2004-09-13)
CDMA2000\CDMA2000_DDC_S3\getDATableWidth.m (669, 2004-09-13)
CDMA2000\CDMA2000_DDC_S3\getSubFilterCoefs.m (474, 2004-09-14)
CDMA2000\CDMA2000_DDC_S3\test\getCoefSet.m (275, 2004-11-16)
CDMA2000\CDMA2000_DDC_S3\test\getDATableValues.m (464, 2004-11-12)
CDMA2000\CDMA2000_DDC_S3\test\getDATableWidth.m (898, 2004-11-22)
CDMA2000\CDMA2000_DDC_S3\test\getSubFilterCoefs.m (474, 2004-11-12)
CDMA2000\CDMA2000_DDC_S3\test\LSsinewaveSNR.m (713, 2005-01-19)
CDMA2000\CDMA2000_DDC_S3\test\sa.m (3622, 2005-01-12)
CDMA2000\CDMA2000_DDC_S3\test\seq_adder.m (69, 2004-10-05)
CDMA2000\CDMA2000_DDC_S3\test\test_CIC.mdl (213544, 2005-01-27)
CDMA2000\CDMA2000_DDC_S3\test\test_CIC_go.m (6040, 2005-02-08)
CDMA2000\CDMA2000_DDC_S3\test\test_Cz.mdl (657324, 2005-02-03)
CDMA2000\CDMA2000_DDC_S3\test\test_Cz_go.m (5801, 2005-02-09)
CDMA2000\CDMA2000_DDC_S3\test\test_Pz.mdl (582949, 2005-02-03)
CDMA2000\CDMA2000_DDC_S3\test\test_Pz_go.m (5775, 2005-02-09)
CDMA2000\CDMA2000_DDC_S3\test\zx.m (288, 2005-01-07)
CDMA2000\CDMA2000_DDC_S3\test\zy.m (288, 2005-01-07)
CDMA2000\CDMA2000_DUC_S3\cdma2000_DUC_4_channel_s3.mdl (1046591, 2005-02-03)
CDMA2000\CDMA2000_DUC_S3\getDATableValues.m (464, 2004-09-13)
CDMA2000\CDMA2000_DUC_S3\getDATableWidth.m (669, 2004-09-13)
CDMA2000\CDMA2000_DUC_S3\getSubFilterCoefs.m (474, 2004-09-14)
CDMA2000\CDMA2000_DUC_S3\LSsinewaveStats.m (1127, 2005-02-09)
CDMA2000\CDMA2000_DUC_S3\seq_adder.m (69, 2004-10-05)
CDMA2000\CDMA2000_DUC_S3\test\getDATableValues.m (464, 2004-09-13)
CDMA2000\CDMA2000_DUC_S3\test\getDATableWidth.m (669, 2004-09-13)
CDMA2000\CDMA2000_DUC_S3\test\getSubFilterCoefs.m (474, 2004-09-14)
CDMA2000\CDMA2000_DUC_S3\test\PNgen.m (3473, 2005-02-02)
CDMA2000\CDMA2000_DUC_S3\test\sa.m (3622, 2005-01-12)
CDMA2000\CDMA2000_DUC_S3\test\seq_adder.m (69, 2004-10-05)
CDMA2000\CDMA2000_DUC_S3\test\test_CIC.mdl (457233, 2005-02-07)
CDMA2000\CDMA2000_DUC_S3\test\test_CIC_go.m (4680, 2005-02-09)
CDMA2000\CDMA2000_DUC_S3\test\test_Pz.mdl (396814, 2005-02-04)
CDMA2000\CDMA2000_DUC_S3\test\test_Pz_go.m (3456, 2005-02-09)
CDMA2000\CDMA2000_DUC_S3\test\zx.m (288, 2005-01-07)
CDMA2000\CDMA2000_DUC_S3\test\zy.m (288, 2005-01-07)
... ...

*********************************************************************** ** ** Xilinx, Inc. 2005 www.xilinx.com ** ** XAPP569 - Digital Up and Down Converters for the CDMA2000 and ** UMTS Base Stations ** *********************************************************************** ** ** Filenames and Descriptions: ** ** CDMA2000_DDC_S3 - CDMA2000 Digital Down Converter for Spartan3/Virtex2 families directory ** CDMA2000_DUC_S3 - CDMA2000 Digital Up Converter for Spartan3/Virtex2 families directory ** UMTS_DDC_S3 - UMTS Digital Down Converter for Spartan3/Virtex2 families directory ** UMTS_DUC_S3 - UMTS Digital Up Converter for Spartan3/Virtex2 families directory ** xapp569.pdf - White paper describing the CDMA2000 and UMTS up and down converter implementations ** ** In each of the directories there is a System Generator reference design model (.mdl) along with some ** associated Matlab (.m) files that are used by the model. The model is a testbench that allows a user ** to drive an input signal into the up/down converter and observe the output. ** ** Each directory also contains a subdirectory called "test" that provides testbenches and associated ** script files that allow a user to test the individual filters used in the up/down converter and observe ** their performance. There is a readme file in each test directory that provides more detail as to how ** to use these test scripts. ** ** Date - version : 02/15/2005 - v1.0 ** ** Author: Xilinx, Inc. ** ** Contact: e-mail hotline@xilinx.com phone + 1 800 255 7778 ** ** Disclaimer: ** LIMITED WARRANTY AND DISCLAIMER. These designs are ** provided to you "as is". Xilinx and its licensors make and you ** receive no warranties or conditions, express, implied, ** statutory or otherwise, and Xilinx specifically disclaims any ** implied warranties of merchantability, non-infringement, or ** fitness for a particular purpose. Xilinx does not warrant that ** the functions contained in these designs will meet your ** requirements, or that the operation of these designs will be ** uninterrupted or error free, or that defects in the Designs ** will be corrected. Furthermore, Xilinx does not warrant or ** make any representations regarding use or the results of the ** use of the designs in terms of correctness, accuracy, ** reliability, or otherwise. ** ** LIMITATION OF LIABILITY. In no event will Xilinx or its ** licensors be liable for any loss of data, lost profits, cost ** or procurement of substitute goods or services, or for any ** special, incidental, consequential, or indirect damages ** arising from the use or operation of the designs or ** accompanying documentation, however caused and on any theory ** of liability. This limitation will apply even if Xilinx ** has been advised of the possibility of such damage. This ** limitation shall apply not-withstanding the failure of the ** essential purpose of any limited remedies herein. ** ** Copyright (c) 2005 Xilinx, Inc. ** All rights reserved ** ********************************************************************************/

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