Jpeg_encode
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：13KB
下载次数：15
上传日期：2010-08-06 08:45:00
上 传 者：
sirdany17
说明： A very good project and very complex. It was written for a bachelor thesis. It does the hardware acceleration to compress an image(jpeg)
文件列表:
cod_diploma\dc_level_shifter.vhd (642, 2010-03-01)
cod_diploma\dwt_conv.vhd (4150, 2010-03-01)
cod_diploma\dwt_lifting.vhd (4000, 2010-03-01)
cod_diploma\dwt_RAM.vhd (5221, 2010-03-01)
cod_diploma\f16_add.vhd (12111, 2010-03-01)
cod_diploma\f16_mul.vhd (2362, 2010-03-01)
cod_diploma\f16_to_i8.vhd (2412, 2010-03-01)
cod_diploma\fifo_2b.vhd (973, 2010-03-01)
cod_diploma\i8_to_f16.vhd (1341, 2010-03-01)
cod_diploma\image_ROM.vhd (5148, 2010-03-01)
cod_diploma\jpeg_2000_top.vhd (11996, 2010-03-01)
cod_diploma\register.vhd (700, 2010-03-01)
cod_diploma\shift_reg.vhd (838, 2010-03-01)
cod_diploma\vga_test.vhd (2610, 2010-03-01)
cod_diploma (0, 2010-04-22)
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