DE2_Default
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：3817KB
下载次数：3
上传日期：2010-08-17 20:01:01
上 传 者：
masterlujp
说明： DE2开发板基本代码 DE2开发板基本代码 DE2开发板基本代码
(basic )
文件列表:
DE2_Default\AUDIO_DAC.v (8754, 2007-06-29)
DE2_Default\Block1.bdf (22267, 2010-07-12)
DE2_Default\db\altsyncram_p132.tdf (106174, 2010-07-20)
DE2_Default\db\altsyncram_upv1.tdf (2870, 2010-07-20)
DE2_Default\db\altsyncram_vpv.tdf (14070, 2010-07-12)
DE2_Default\db\DE2_Default.(0).cnf.cdb (10390, 2010-08-04)
DE2_Default\db\DE2_Default.(0).cnf.hdb (6622, 2010-08-04)
DE2_Default\db\DE2_Default.(1).cnf.cdb (1608, 2010-07-20)
DE2_Default\db\DE2_Default.(1).cnf.hdb (1111, 2010-07-20)
DE2_Default\db\DE2_Default.(10).cnf.cdb (1424, 2010-07-20)
DE2_Default\db\DE2_Default.(10).cnf.hdb (566, 2010-07-20)
DE2_Default\db\DE2_Default.(11).cnf.cdb (21915, 2010-07-20)
DE2_Default\db\DE2_Default.(11).cnf.hdb (2034, 2010-07-20)
DE2_Default\db\DE2_Default.(12).cnf.cdb (12950, 2010-07-20)
DE2_Default\db\DE2_Default.(12).cnf.hdb (5538, 2010-07-20)
DE2_Default\db\DE2_Default.(13).cnf.cdb (12954, 2010-07-20)
DE2_Default\db\DE2_Default.(13).cnf.hdb (5538, 2010-07-20)
DE2_Default\db\DE2_Default.(14).cnf.cdb (213992, 2010-07-20)
DE2_Default\db\DE2_Default.(14).cnf.hdb (14359, 2010-07-20)
DE2_Default\db\DE2_Default.(15).cnf.cdb (31620, 2010-07-20)
DE2_Default\db\DE2_Default.(15).cnf.hdb (2405, 2010-07-20)
DE2_Default\db\DE2_Default.(16).cnf.cdb (7974, 2010-07-20)
DE2_Default\db\DE2_Default.(16).cnf.hdb (1860, 2010-07-20)
DE2_Default\db\DE2_Default.(17).cnf.cdb (6613, 2010-07-20)
DE2_Default\db\DE2_Default.(17).cnf.hdb (1850, 2010-07-20)
DE2_Default\db\DE2_Default.(18).cnf.cdb (14209, 2010-07-20)
DE2_Default\db\DE2_Default.(18).cnf.hdb (4403, 2010-07-20)
DE2_Default\db\DE2_Default.(19).cnf.cdb (7597, 2010-08-04)
DE2_Default\db\DE2_Default.(19).cnf.hdb (1850, 2010-08-04)
DE2_Default\db\DE2_Default.(2).cnf.cdb (1731, 2010-07-20)
DE2_Default\db\DE2_Default.(2).cnf.hdb (1186, 2010-07-20)
DE2_Default\db\DE2_Default.(20).cnf.cdb (4447, 2010-08-04)
DE2_Default\db\DE2_Default.(20).cnf.hdb (1440, 2010-08-04)
DE2_Default\db\DE2_Default.(3).cnf.cdb (1803, 2010-07-20)
DE2_Default\db\DE2_Default.(3).cnf.hdb (1277, 2010-07-20)
DE2_Default\db\DE2_Default.(4).cnf.cdb (2048, 2010-07-20)
DE2_Default\db\DE2_Default.(4).cnf.hdb (1254, 2010-07-20)
DE2_Default\db\DE2_Default.(5).cnf.cdb (1166, 2010-07-20)
DE2_Default\db\DE2_Default.(5).cnf.hdb (743, 2010-07-20)
DE2_Default\db\DE2_Default.(6).cnf.cdb (14901, 2010-07-20)
... ...
DE2_Default
-----------
This design is the initial design when the board is powered-up. It increments a counter and displays the value on the
7-segment displays and LEDs. An image is also displayed on the VGA port.
Running the Design
------------------
1) Launch the Quartus II software.
2) Open the DE2_Default.qpf project located in the \DE2_Default folder. (File menu -> Open Project)
3) Open the Programmer window. (Tools menu -> Programmer)
4) The DE2_Default.sof programming file should be listed.
Check the 'Program/Configure' box and set up the JTAG programming hardware connection via the 'Hardware Setup' button.
5) Press 'Start' to start programming. The design should now be programmed and running.
User Inputs to the Design
-------------------------
None.
Compiling the Design
--------------------
1) Launch the Quartus II software.
2) Open the DE2_Default.qpf project located in the \DE2_Default folder. (File menu -> Open Project)
3) Start compilation. (Processing -> Start Compilation)
4) After compilation is finished, you can run the design with the generated SOF file. See 'Running the Design' above.
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