vhdl
所属分类:VHDL/FPGA/Verilog
开发工具:Others
文件大小:5KB
下载次数:2
上传日期:2010-08-22 19:35:27
上 传 者:
devinesong
说明: 当接收到一个信号(D_start)时,开始计时,再收到另一个信号(D_stop)时,计时结束,得到计时时间A,然后将时间A与给定时间B进行比较,如果小于时间B,程序结束,进行下一环节(LED),否则返回重新等待计时(cnt:=0)
(When receiving a signal (D_start), the start time, and then received another signal (D_stop), the time the end of time by time A, then the time A and B compare a given time, if less than the time B, end of the process, proceed to the next link (LED), or return to re-wait time (cnt: = 0))
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vhdl.doc (27136, 2010-08-21)
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