jianxiang
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：20606KB
下载次数：45
上传日期：2010-08-24 13:04:39
上 传 者：
aajj
说明： 基于ISE的鉴频、鉴相器，开发板：xilinx公司spartan 3E 500.精确度1hz,1度。完全正确。
(Based on ISE' s Kam-frequency phase detector, development board: xilinx company spartan 3E 500. Precision 1hz, 1 degree. Entirely correct.)
文件列表:
jianxiang\mymodel\model\bitgen.xmsgs (1518, 2010-05-14)
jianxiang\mymodel\model\ChipS_1.cdc (4070, 2010-05-14)
jianxiang\mymodel\model\clk7seg.vhd (3317, 2010-05-16)
jianxiang\mymodel\model\clk7seg_wrapper.ngc (81467, 2010-05-14)
jianxiang\mymodel\model\clock_generator_0_wrapper.ngc (4268, 2010-05-14)
jianxiang\mymodel\model\device_usage_statistics.html (89077, 2010-05-14)
jianxiang\mymodel\model\dlmb_cntlr_wrapper.ngc (12903, 2010-05-14)
jianxiang\mymodel\model\dlmb_wrapper.ngc (12139, 2010-05-14)
jianxiang\mymodel\model\edkBmmFile.bmm (1298, 2010-05-16)
jianxiang\mymodel\model\edkBmmFile_bd.bmm (2267, 2010-05-16)
jianxiang\mymodel\model\ilmb_cntlr_wrapper.ngc (12903, 2010-05-14)
jianxiang\mymodel\model\ilmb_wrapper.ngc (12138, 2010-05-14)
jianxiang\mymodel\model\in_first_wrapper.ngc (108148, 2010-05-14)
jianxiang\mymodel\model\in_second_wrapper.ngc (108856, 2010-05-14)
jianxiang\mymodel\model\in_third_wrapper.ngc (108143, 2010-05-14)
jianxiang\mymodel\model\jiping.v (533, 2010-05-13)
jianxiang\mymodel\model\jiping.vhd (806, 2010-05-14)
jianxiang\mymodel\model\leds_8bit_wrapper.ngc (63250, 2010-05-14)
jianxiang\mymodel\model\lmb_bram_wrapper.ngc (44027, 2010-05-14)
jianxiang\mymodel\model\map.xmsgs (2448, 2010-05-14)
jianxiang\mymodel\model\mb_plb_wrapper.ngc (273372, 2010-05-14)
jianxiang\mymodel\model\mdm_0_wrapper.ngc (108406, 2010-05-14)
jianxiang\mymodel\model\microblaze\blockdiagram\.dswkshop\MdtSvgBLKD_Dimensions.xsl (7376, 2010-05-11)
jianxiang\mymodel\model\microblaze\blockdiagram\.dswkshop\MdtSvgDiag_Colors.xsl (5542, 2010-05-11)
jianxiang\mymodel\model\microblaze\blockdiagram\.dswkshop\MdtSvgDiag_Globals.xsl (1103, 2010-05-11)
jianxiang\mymodel\model\microblaze\blockdiagram\.dswkshop\MdtSvgDiag_StyleDefs.css (9011, 2010-05-11)
jianxiang\mymodel\model\microblaze\blockdiagram\.dswkshop\MdtTinySvgBLKD_BusLaneSpaces.xsl (125726, 2010-05-11)
jianxiang\mymodel\model\microblaze\blockdiagram\.dswkshop\MdtTinySvgBLKD_Busses.xsl (19265, 2010-05-11)
jianxiang\mymodel\model\microblaze\blockdiagram\.dswkshop\MdtTinySvgBLKD_Functions.xsl (39984, 2010-05-11)
jianxiang\mymodel\model\microblaze\blockdiagram\.dswkshop\MdtTinySvgBLKD_Globals.xsl (5797, 2010-05-11)
jianxiang\mymodel\model\microblaze\blockdiagram\.dswkshop\MdtTinySvgBLKD_IOPorts.xsl (19244, 2010-05-11)
jianxiang\mymodel\model\microblaze\blockdiagram\.dswkshop\MdtTinySvgBLKD_Main.xsl (52720, 2010-05-11)
jianxiang\mymodel\model\microblaze\blockdiagram\.dswkshop\MdtTinySvgBLKD_Peripherals.xsl (58008, 2010-05-11)
jianxiang\mymodel\model\microblaze\blockdiagram\.dswkshop\MdtTinySvgBLKD_Processors.xsl (16961, 2010-05-11)
jianxiang\mymodel\model\microblaze\blockdiagram\.dswkshop\MdtTinySvgBLKD_StyleDefs.xsl (17598, 2010-05-11)
jianxiang\mymodel\model\microblaze\blockdiagram\.dswkshop\MdtTinySvgDiag_BifShapes.xsl (7645, 2010-05-11)
jianxiang\mymodel\model\microblaze\blockdiagram\.dswkshop\MdtXdsGen_Colors.xsl (4600, 2010-05-11)
jianxiang\mymodel\model\microblaze\blockdiagram\.dswkshop\MdtXdsGen_Globals.xsl (3658, 2010-05-11)
jianxiang\mymodel\model\microblaze\blockdiagram\.dswkshop\MdtXdsGen_HTMLDatasheet.css (2446, 2010-05-11)
jianxiang\mymodel\model\microblaze\blockdiagram\.dswkshop\MdtXdsGen_HTMLDatasheet.xsl (58938, 2010-05-11)
... ...
The following files were generated for 'icon_pro' in directory
E:\jianxiang\mymodel\model\_ngo\cs_icon_pro\
icon_pro.gise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
icon_pro.ise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
icon_pro.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
icon_pro.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
icon_pro.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
icon_pro.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
icon_pro.xise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
icon_pro_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
icon_pro_readme.txt:
Text file indicating the files generated and how they are used.
icon_pro_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
近期下载者：
相关文件：
收藏者：