sdram
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：3637KB
下载次数：7
上传日期：2010-09-21 15:37:15
上 传 者：
firstepgtr
说明： 文件中包含Sdram的Verilog程序以及很全的Sdram的资料
(Sdram the Verilog file contains procedures and information are all of Sdram)
文件列表:
sdram_paul\256Mb_sdr.pdf (3686773, 2010-08-10)
sdram_paul\sdram_controller_verilog_lattice.pdf (198140, 2009-09-06)
sdram_paul\sdram_controller_xm\docs\filelist.txt (897, 2005-05-11)
sdram_paul\sdram_controller_xm\docs\user's guide.doc (427520, 2005-05-11)
sdram_paul\sdram_controller_xm\par\xm\sdr_top.log (99, 2005-03-10)
sdram_paul\sdram_controller_xm\par\xm\sdr_top.mrp (53550, 2005-03-10)
sdram_paul\sdram_controller_xm\par\xm\sdr_top.pad (38054, 2005-03-10)
sdram_paul\sdram_controller_xm\par\xm\sdr_top.par (4348, 2005-03-10)
sdram_paul\sdram_controller_xm\par\xm\sdr_top.prf (356, 2005-03-10)
sdram_paul\sdram_controller_xm\par\xm\sdr_top.sdf (110563, 2005-03-10)
sdram_paul\sdram_controller_xm\par\xm\sdr_top.tcl (6916, 2005-03-10)
sdram_paul\sdram_controller_xm\par\xm\sdr_top.vo (146769, 2005-03-10)
sdram_paul\sdram_controller_xm\par\xm\sdr_top_overconstraint.twr (6548, 2005-03-10)
sdram_paul\sdram_controller_xm\par\xm\sdr_top_post.prf (358, 2005-03-10)
sdram_paul\sdram_controller_xm\par\xm\sdr_top_post_route_trace.twr (4592, 2005-03-10)
sdram_paul\sdram_controller_xm\simulation\xm\modelsim\rtl\rtl_sim.log (4648, 2004-06-22)
sdram_paul\sdram_controller_xm\simulation\xm\modelsim\scripts\sdr_fsim.tcl (576, 2004-06-22)
sdram_paul\sdram_controller_xm\simulation\xm\modelsim\scripts\sdr_tsim.tcl (445, 2005-01-19)
sdram_paul\sdram_controller_xm\simulation\xm\modelsim\timing\timing_sim.log (32860, 2004-06-23)
sdram_paul\sdram_controller_xm\source\sdr_ctrl.v (9867, 2004-06-29)
sdram_paul\sdram_controller_xm\source\sdr_data.v (5244, 2004-06-29)
sdram_paul\sdram_controller_xm\source\sdr_par.v (7336, 2004-06-29)
sdram_paul\sdram_controller_xm\source\sdr_sig.v (7843, 2004-06-29)
sdram_paul\sdram_controller_xm\source\sdr_top.v (5256, 2004-06-29)
sdram_paul\sdram_controller_xm\synthesis\xm\synplicity\rev_1\sdr_top.edn (173573, 2005-01-19)
sdram_paul\sdram_controller_xm\synthesis\xm\synplicity\rev_1\sdr_top.prf (5040, 2005-01-19)
sdram_paul\sdram_controller_xm\synthesis\xm\synplicity\rev_1\sdr_top.tlg (855, 2005-01-19)
sdram_paul\sdram_controller_xm\synthesis\xm\synplicity\sdr_top.prd (318, 2005-01-19)
sdram_paul\sdram_controller_xm\synthesis\xm\synplicity\sdr_top.prj (1346, 2005-01-19)
sdram_paul\sdram_controller_xm\synthesis\xm\synplicity\sdr_top.tcl (1488, 2005-02-22)
sdram_paul\sdram_controller_xm\testbench\sdr_tb.tf (13905, 2004-08-19)
sdram_paul\W986416_75.pdf (2102336, 2010-08-19)
sdram_paul\sdram_controller_xm\simulation\xm\modelsim\rtl (0, 2010-08-30)
sdram_paul\sdram_controller_xm\simulation\xm\modelsim\scripts (0, 2010-08-30)
sdram_paul\sdram_controller_xm\simulation\xm\modelsim\timing (0, 2010-08-30)
sdram_paul\sdram_controller_xm\synthesis\xm\synplicity\rev_1 (0, 2010-08-30)
sdram_paul\sdram_controller_xm\simulation\xm\modelsim (0, 2010-08-30)
... ...
File List
1. /docs/filelist.txt --> Reference Design directory filelist
/docs/user's guide.doc --> USER GUIDE document
/docs/ReadMe.txt --> Read me file
2. /par/xm/synplicity/sdr_top.prf --> Preference file to constrain frequent to 190MHz
3. /simulation/xm/modelsim/scripts/sdr_fsim.tcl --> Scripts for RTL simulation
/simulation/xm/modelsim/scripts/sdr_tsim.tcl --> Scripts for timing simulation
4. /synthesis/xm/synplicity/sdr_top.tcl --> Scripts for synthesis using synplify
6. /testbench/sdr_tb.tf --> Testbench for simulation
Simulation
1. Launch modelsim oem edition.
2. Click [File] --> [Change Directory...] and select "/simulation/xm/modelsim/scripts".
3. Click [Tools] --> [Excute Macro]
For RTL simulation, select "/simulation/modelsim/scripts/sdr_fsim.tcl"
(if you want to do timing simulation, select "/simulation/modelsim/xm/scripts/sdr_tsim.tcl",
and remember do synthesis and PAR first).
Note: If you want to use a full-up version modesim, you will need to compile the MAGMA device library source
available in ispLEVER software.
Synthesis
1. Launch synplify.
2. Select Lattice XP, LFXP10E device.
3. Click [Run] -> [Run Tcl Scripts] and select /synthesis/xm/synplicity/sdr_top.tcl.
PAR
You can run PAR in two ways:
1) 1. Launch ispLEVER Tcl Editor.
2. Click [File] -> [Open...] and select /par/xm/sdr_top.tcl in your own directory.
3. in the tcl file line 4, replace the "e:/ref_design/sdram_controller/par/xm" with your own directory,
4. Click [Run] -> [Start] to run the whole flow.
5. Check the "sdr_top.mrp" and "sdr_top_post_route_trace.twr" to check the map and the performance report.
2) 1. Launch ispLEVER.
2. Create a new project in "/par/xm" under your own DIR and name it sdr_top, select EDIF type.
3. Select device as "LFXP10E -5F672CES". (Lattice-XP, LFXP10E, -5, FPBGA672)
4. Import source file from "/synthesis/xm/synplicity/rev_1/sdr_top.edn".
5. Click "Place and Route" on right panel to run PAR.
(Click "Generate Timing Simulation File" on right pannel if you want to do timing simulation).
6. Click [Source] -> [Import Constraint File], select sdr_top_post.prf.
7. Click "Place and Route Trace Report" on right panel to check the performance result.
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