TestAD9709_AD9288_Verilog
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：2081KB
下载次数：133
上传日期：2010-10-01 16:25:16
上 传 者：
luno1
说明： 使用Verilog语言控制高速AD9288 Ad9707
(Verilog language control using high-speed AD9288 Ad9707)
文件列表:
TestAD9709_AD9288_Verilog\.sopc_builder\filters.xml (65, 2010-09-17)
TestAD9709_AD9288_Verilog\db\altsyncram_0to3.tdf (13603, 2010-07-18)
TestAD9709_AD9288_Verilog\db\altsyncram_mvo3.tdf (39678, 2010-07-20)
TestAD9709_AD9288_Verilog\db\altsyncram_ovo3.tdf (30990, 2010-07-19)
TestAD9709_AD9288_Verilog\db\altsyncram_sso3.tdf (13597, 2010-07-18)
TestAD9709_AD9288_Verilog\db\altsyncram_svo3.tdf (30997, 2010-07-19)
TestAD9709_AD9288_Verilog\db\altsyncram_uvo3.tdf (22309, 2010-07-19)
TestAD9709_AD9288_Verilog\db\cmpr_j4c.tdf (1590, 2010-07-18)
TestAD9709_AD9288_Verilog\db\cmpr_n4c.tdf (1912, 2010-07-18)
TestAD9709_AD9288_Verilog\db\cntr_4ti.tdf (4651, 2010-07-18)
TestAD9709_AD9288_Verilog\db\cntr_84i.tdf (4248, 2010-07-18)
TestAD9709_AD9288_Verilog\db\cntr_a4i.tdf (3505, 2010-07-20)
TestAD9709_AD9288_Verilog\db\cntr_b4i.tdf (3275, 2010-07-19)
TestAD9709_AD9288_Verilog\db\cntr_c4i.tdf (4248, 2010-07-18)
TestAD9709_AD9288_Verilog\db\cntr_d4i.tdf (4248, 2010-07-19)
TestAD9709_AD9288_Verilog\db\cntr_iti.tdf (5130, 2010-07-18)
TestAD9709_AD9288_Verilog\db\cntr_r2i.tdf (3044, 2010-07-18)
TestAD9709_AD9288_Verilog\db\cntr_umi.tdf (3315, 2010-07-18)
TestAD9709_AD9288_Verilog\db\decode_9jf.tdf (1559, 2010-07-18)
TestAD9709_AD9288_Verilog\db\mux_lgc.tdf (4423, 2010-07-18)
TestAD9709_AD9288_Verilog\db\mux_pgc.tdf (5015, 2010-07-18)
TestAD9709_AD9288_Verilog\db\prev_cmp_TestAD9709_AD9288.asm.qmsg (2043, 2010-09-18)
TestAD9709_AD9288_Verilog\db\prev_cmp_TestAD9709_AD9288.eda.qmsg (2244, 2010-09-18)
TestAD9709_AD9288_Verilog\db\prev_cmp_TestAD9709_AD9288.fit.qmsg (61976, 2010-09-18)
TestAD9709_AD9288_Verilog\db\prev_cmp_TestAD9709_AD9288.map.qmsg (17909, 2010-09-18)
TestAD9709_AD9288_Verilog\db\prev_cmp_TestAD9709_AD9288.qmsg (160638, 2010-09-18)
TestAD9709_AD9288_Verilog\db\prev_cmp_TestAD9709_AD9288.tan.qmsg (76234, 2010-09-18)
TestAD9709_AD9288_Verilog\db\TestAD9709_AD9288.(0).cnf.cdb (3227, 2010-09-18)
TestAD9709_AD9288_Verilog\db\TestAD9709_AD9288.(0).cnf.hdb (1984, 2010-09-18)
TestAD9709_AD9288_Verilog\db\TestAD9709_AD9288.(1).cnf.cdb (4747, 2010-09-17)
TestAD9709_AD9288_Verilog\db\TestAD9709_AD9288.(1).cnf.hdb (2168, 2010-09-17)
TestAD9709_AD9288_Verilog\db\TestAD9709_AD9288.(10).cnf.cdb (2312, 2010-09-17)
TestAD9709_AD9288_Verilog\db\TestAD9709_AD9288.(10).cnf.hdb (680, 2010-09-17)
TestAD9709_AD9288_Verilog\db\TestAD9709_AD9288.(11).cnf.cdb (10075, 2010-09-17)
TestAD9709_AD9288_Verilog\db\TestAD9709_AD9288.(11).cnf.hdb (2854, 2010-09-17)
TestAD9709_AD9288_Verilog\db\TestAD9709_AD9288.(12).cnf.cdb (2313, 2010-09-17)
TestAD9709_AD9288_Verilog\db\TestAD9709_AD9288.(12).cnf.hdb (680, 2010-09-17)
TestAD9709_AD9288_Verilog\db\TestAD9709_AD9288.(13).cnf.cdb (2237, 2010-09-17)
TestAD9709_AD9288_Verilog\db\TestAD9709_AD9288.(13).cnf.hdb (770, 2010-09-17)
TestAD9709_AD9288_Verilog\db\TestAD9709_AD9288.(14).cnf.cdb (2595, 2010-09-17)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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