mem32_to_pcitarget_verilog
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：20KB
下载次数：21
上传日期：2010-10-11 15:15:07
上 传 者：
agroloft
说明： This design example shows how to implement interface between 32-bit pci target Altera megafunction instantiation and a 32-bit synchronous memory
文件列表:
mem32_to_pcitarget_verilog\mem256x32.v (7346, 2004-12-30)
mem32_to_pcitarget_verilog\pt32.v (22400, 2009-10-23)
mem32_to_pcitarget_verilog\pt32.vo (98833, 2009-10-23)
mem32_to_pcitarget_verilog\targ_mem32.v (3127, 2010-10-11)
mem32_to_pcitarget_verilog\top_t32.v (2794, 2010-10-11)
mem32_to_pcitarget_verilog (0, 2009-12-21)
Target MemoryExamples for MT32and T32 v1.0.0 Readme file
The design example shows how to interface Altera's 32-bit Target MegaCore functions to a synchronous memory similar to altsyncram.
Package Contents
================
The zip file includes the following Verilog files
o mem256x32.v - 256x32 altsynram
o targ_mem32. v - Top level user design
o pt32.v - 32-bit PCI target
o pt32.vo - Verilog functional simulation models for the PCI target
o top_t32.v - Top level for this design example and instantiates the above 2 modules.
Software Tool Requirements
==========================
o Quartus II software version 4.2 or later
o PCI Compiler version 3.2.0 or later
Version 1.0.0
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