sp601_MIG_rdf0005_12.2
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：4479KB
下载次数：68
上传日期：2010-10-26 15:34:31
上 传 者：
supperpippo123
说明： spartan—6fpga 用mig生成ddr2接口的ip核，用户可以直接调用此ip控制ddr2
(spartan-6fpga generated by mig ddr2 interface ip core, the user can call this ip control ddr2)
文件列表:
mig_v3_5\example_design\par\example_top.bit (464310, 2010-07-10)
mig_v3_5\example_design\par\example_top.cdc (13980, 2010-07-08)
mig_v3_5\example_design\par\example_top.ucf (10731, 2010-07-08)
mig_v3_5\example_design\rtl\example_top.v (26943, 2010-07-09)
mig_v3_5\example_design\rtl\mcb_raw_wrapper.v (261159, 2010-07-10)
mig_v3_5\example_design\rtl\memc3_tb_top.v (12503, 2010-07-09)
ready_for_download\example_top.bit (464310, 2010-07-10)
ready_for_download\make_download_files.bat (60, 2010-07-10)
ready_for_download\sp601_12.2.cpj (71444, 2010-07-13)
sp601_mig_prebuilt_example_design\mig_v3_5.gise (1059, 2010-07-08)
sp601_mig_prebuilt_example_design\mig_v3_5.veo (6862, 2010-07-08)
sp601_mig_prebuilt_example_design\mig_v3_5.xco (1216, 2010-07-08)
sp601_mig_prebuilt_example_design\mig_v3_5.xise (42482, 2010-07-08)
sp601_mig_prebuilt_example_design\mig_v3_5\docs\ug388.pdf (2171751, 2010-06-15)
sp601_mig_prebuilt_example_design\mig_v3_5\docs\ug416.pdf (4206757, 2010-03-22)
sp601_mig_prebuilt_example_design\mig_v3_5\example_design\datasheet.txt (2346, 2010-07-08)
sp601_mig_prebuilt_example_design\mig_v3_5\example_design\log.txt (2650, 2010-07-08)
sp601_mig_prebuilt_example_design\mig_v3_5\example_design\mig.prj (2862, 2010-07-08)
sp601_mig_prebuilt_example_design\mig_v3_5\example_design\par\create_ise.bat (3265, 2010-07-08)
sp601_mig_prebuilt_example_design\mig_v3_5\example_design\par\example_top.bit (464310, 2010-07-10)
sp601_mig_prebuilt_example_design\mig_v3_5\example_design\par\example_top.cdc (13980, 2010-07-08)
sp601_mig_prebuilt_example_design\mig_v3_5\example_design\par\example_top.ncd (1302650, 2010-07-10)
sp601_mig_prebuilt_example_design\mig_v3_5\example_design\par\example_top.pad (15723, 2010-07-10)
sp601_mig_prebuilt_example_design\mig_v3_5\example_design\par\example_top.par (19356, 2010-07-10)
sp601_mig_prebuilt_example_design\mig_v3_5\example_design\par\example_top.ucf (10731, 2010-07-08)
sp601_mig_prebuilt_example_design\mig_v3_5\example_design\par\example_top_map.mrp (231932, 2010-07-10)
sp601_mig_prebuilt_example_design\mig_v3_5\example_design\par\icon_coregen.xco (1371, 2010-07-08)
sp601_mig_prebuilt_example_design\mig_v3_5\example_design\par\ila_coregen.xco (3860, 2010-07-08)
sp601_mig_prebuilt_example_design\mig_v3_5\example_design\par\ise_flow.bat (4053, 2010-07-08)
sp601_mig_prebuilt_example_design\mig_v3_5\example_design\par\ise_run.txt (1214, 2010-07-08)
sp601_mig_prebuilt_example_design\mig_v3_5\example_design\par\makeproj.bat (28, 2010-07-08)
sp601_mig_prebuilt_example_design\mig_v3_5\example_design\par\mem_interface_top.ut (385, 2010-07-08)
sp601_mig_prebuilt_example_design\mig_v3_5\example_design\par\rem_files.bat (7956, 2010-07-08)
sp601_mig_prebuilt_example_design\mig_v3_5\example_design\par\set_ise_prop.tcl (5762, 2010-07-08)
sp601_mig_prebuilt_example_design\mig_v3_5\example_design\par\vio_coregen.xco (1559, 2010-07-08)
sp601_mig_prebuilt_example_design\mig_v3_5\example_design\rtl\example_top.v (26943, 2010-07-09)
sp601_mig_prebuilt_example_design\mig_v3_5\example_design\rtl\iodrp_controller.v (11430, 2010-06-03)
sp601_mig_prebuilt_example_design\mig_v3_5\example_design\rtl\iodrp_mcb_controller.v (15423, 2010-03-22)
... ...
*******************************************************************************
** Copyright 2010 Xilinx, Inc. All rights reserved.
** This file contains confidential and proprietary information of Xilinx, Inc. and
** is protected under U.S. and international copyright and other intellectual property laws.
*******************************************************************************
** ____ ____
** / /\/ /
** /___/ \ / Vendor: Xilinx
** \ \ \/
** \ \ readme.txt
** / /
** /___/ /\
** \ \ / \ Associated Filename:
** \___\/\___\
**
** Device: Spartan-6 FPGA
** Purpose:XTP039 is a MIG Design creation tutorial for the SP601 evaluation board.
**
** Reference: xtp039.pdf
**
**
*******************************************************************************
**
** Disclaimer:
**
** This disclaimer is not a license and does not grant any rights to the materials
** distributed herewith. Except as otherwise provided in a valid license issued to you
** by Xilinx, and to the maximum extent permitted by applicable law:
** (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
** AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
** INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
** FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
** or tort, including negligence, or under any other theory of liability) for any loss or damage
** of any kind or nature related to, arising under or in connection with these materials,
** including for any direct, or any indirect, special, incidental, or consequential loss
** or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
** as a result of any action brought by a third party) even if such damage or loss was
** reasonably foreseeable or Xilinx had been advised of the possibility of the same.
** Critical Applications:
**
** Xilinx products are not designed or intended to be fail-safe, or for use in any application
** requiring fail-safe performance, such as life-support or safety devices or systems,
** Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
** or any other applications that could lead to death, personal injury, or severe property or
** environmental damage (individually and collectively, "Critical Applications"). Customer assumes
** the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
** to applicable laws and regulations governing limitations on product liability.
** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
*******************************************************************************
** IMPORTANT NOTES **
The SP601 DDR2 Memory Demonstration step-by-step instructions are described in xtp039.pdf
These files have AR34089 applied.
http://www.xilinx.com/support/answers/34089.htm
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