文件列表:

ssss\ddr2_sdram\folder_details.txt (1697, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\datasheet.txt (2207, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\design_testing.txt (1379, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\par\create_ise.bat (147, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\par\icon_coregen.xco (1374, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\par\ila_coregen.xco (3863, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\par\ise_flow.bat (886, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\par\ise_run.txt (1290, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\par\makeproj.bat (26, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\par\mem_interface_top.ut (389, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\par\set_ise_prop.tcl (7082, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\par\vio_coregen.xco (1560, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\par\vlog_bl8.bit (341690, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\par\vlog_bl8.cdc (4691, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\par\vlog_bl8.ucf (43124, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\rtl\vlog_bl8.v (11792, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\rtl\vlog_bl8_addr_gen_0.v (6962, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\rtl\vlog_bl8_cal_ctl.v (7142, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\rtl\vlog_bl8_cal_top.v (4107, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\rtl\vlog_bl8_clk_dcm.v (3802, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\rtl\vlog_bl8_cmd_fsm_0.v (7652, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\rtl\vlog_bl8_cmp_data_0.v (5083, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\rtl\vlog_bl8_controller_0.v (43293, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\rtl\vlog_bl8_controller_iobs_0.v (7154, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\rtl\vlog_bl8_data_gen_0.v (4197, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\rtl\vlog_bl8_data_path_0.v (6420, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\rtl\vlog_bl8_data_path_iobs_0.v (5669, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\rtl\vlog_bl8_data_read_0.v (7920, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\rtl\vlog_bl8_data_read_controller_0.v (7544, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\rtl\vlog_bl8_data_write_0.v (6105, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\rtl\vlog_bl8_dqs_delay.v (3889, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\rtl\vlog_bl8_fifo_0_wr_en_0.v (3148, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\rtl\vlog_bl8_fifo_1_wr_en_0.v (3250, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\rtl\vlog_bl8_infrastructure.v (3419, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\rtl\vlog_bl8_infrastructure_iobs_0.v (4078, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\rtl\vlog_bl8_infrastructure_top.v (7758, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\rtl\vlog_bl8_iobs_0.v (6817, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\rtl\vlog_bl8_main_0.v (7866, 2010-07-08)
ssss\ddr2_sdram\verilog\vlog_bl8\example_design\rtl\vlog_bl8_parameters_0.v (4339, 2010-07-08)
... ...

1. Spartan-3A Starter Kit supports DDR2 SDRAM(Components) memory design for Spartan-3A FPGA xc3s700afg484. 2. Above mentioned design were generated at 133MHz clock frequency. 3. You should go through the readme files provided in the corresponding design folders before using the bit files for testing Spartan-3A Starter Kit. 4. All the designs use the 133MHz onboard clock source as the design clock source. All designs are verified with ISE 12.2. 5. Steps to regenerate for other frequencies using SMA connector, a) Uncomment the LOC constraints for external clock and comment the on board clock in UCF file. #NET "sys_clk" LOC = "V12"; # on board clock NET "sys_clk" LOC = "U12"; #external clock 6. Users can also regenerate the bit files by running PAR with the help of ise_flow.bat batch file or create_ise.bat file provided in the correspondng design folders. Refer to the readme.txt file provided in the par folder of the respective design folders. 7. When you simulate the VHDL designs, you will be reported a warning message by Modelsim that "# ** Warning: (vsim-3473) Component instance "i_icon : icon is not bound.". You can safely ignore this warning since these component instances are used for probing internal design signals on to Chipscope. 8. Please contact support.xilinx.com for Spartan-3A Starter Kit details.

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