Three-stage-state-machine

所属分类:VHDL/FPGA/Verilog
开发工具:PDF
文件大小:288KB
下载次数:12
上传日期:2010-11-01 22:36:07
上 传 者tiantao606
说明:  状态机是逻辑设计的重要内容,状态机的设计水平直接反应工程师的逻辑功底,所以许 多公司的硬件和逻辑工程师面试中,状态机设计几乎是必选题目。本章在引入状态机设计思想的基础上,重点讨论如何写好状态机。
(State machine is an important part of logic design, state machine design engineers a direct response to the logic level of skills, so the company s hardware and logic more than engineers interview, state machine design is almost must-topic. The introduction of this chapter, the state machine design thinking Like basis, focused on how to write a state machine.)

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Three-stage-state-machine.pdf (340151, 2006-08-09)

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