文件列表:

RD1065\docs (0, 2010-03-04)
RD1065\docs\rd1065.pdf (285631, 2010-03-04)
RD1065\project (0, 2010-02-26)
RD1065\project\4kze (0, 2010-02-26)
RD1065\project\4kze\verilog (0, 2010-03-03)
RD1065\project\4kze\verilog\gpio.lci (1828, 2010-03-02)
RD1065\project\4kze\verilog\gpio.syn (381, 2010-02-26)
RD1065\project\4kze\verilog\gpio_test_tfa.udo (693, 2010-03-03)
RD1065\project\4kze\verilog\gpio_test_tffa.udo (911, 2010-03-02)
RD1065\project\4kze\vhdl (0, 2010-03-03)
RD1065\project\4kze\vhdl\gpio.lci (1821, 2010-03-02)
RD1065\project\4kze\vhdl\gpio.syn (368, 2010-03-02)
RD1065\project\4kze\vhdl\gpio_test_vhda.udo (783, 2010-03-02)
RD1065\project\4kze\vhdl\gpio_test_vhdaf.udo (980, 2010-03-02)
RD1065\project\xo (0, 2010-02-26)
RD1065\project\xo\verilog (0, 2010-02-26)
RD1065\project\xo\verilog\gpio.lpf (124, 2010-02-26)
RD1065\project\xo\verilog\gpio.syn (404, 2010-02-25)
RD1065\project\xo\verilog\gpio_test_tf.udo (829, 2010-03-03)
RD1065\project\xo\verilog\gpio_test_tff.udo (907, 2010-03-02)
RD1065\project\xo\verilog\gpio_test_tfr.udo (705, 2010-03-02)
RD1065\project\xo\vhdl (0, 2010-02-26)
RD1065\project\xo\vhdl\gpio.lpf (126, 2010-02-26)
RD1065\project\xo\vhdl\gpio.syn (480, 2010-02-25)
RD1065\project\xo\vhdl\gpio_test_vhd.udo (752, 2010-03-02)
RD1065\project\xo\vhdl\gpio_test_vhdf.udo (965, 2010-03-02)
RD1065\project\xo\vhdl\gpio_test_vhdr.udo (742, 2010-03-02)
RD1065\project\xp2 (0, 2010-02-26)
RD1065\project\xp2\verilog (0, 2010-02-26)
RD1065\project\xp2\verilog\gpio.lpf (124, 2010-02-26)
RD1065\project\xp2\verilog\gpio.syn (404, 2010-02-26)
RD1065\project\xp2\verilog\gpio_test_tf.udo (689, 2010-03-02)
RD1065\project\xp2\verilog\gpio_test_tff.udo (907, 2010-03-02)
RD1065\project\xp2\verilog\gpio_test_tfr.udo (705, 2010-03-02)
RD1065\project\xp2\vhdl (0, 2010-02-26)
RD1065\project\xp2\vhdl\gpio.lpf (126, 2010-02-26)
RD1065\project\xp2\vhdl\gpio.syn (480, 2010-02-26)
RD1065\project\xp2\vhdl\gpio_test_vhd.udo (752, 2010-03-02)
RD1065\project\xp2\vhdl\gpio_test_vhdf.udo (962, 2010-03-02)
... ...

CPU GPIO Reference Design =============================================================================== File List 1. /docs/rd1065.pdf --> CPU GPIO reference design document /docs/rd1065_readme.txt --> Read me file (this file) 2. /project/4kze/verilog/gpio.syn --> ispLEVER Classic project file /project/4kze/verilog/gpio.lci --> preference file /project/4kze/verilog/gpio_test_tffa.udo --> script for Verilog functional simulation with Active HDL /project/4kze/verilog/gpio_test_tfa.udo --> script for Verilog timing simulation with Active HDL /project/4kze/vhdl/gpio.syn --> ispLEVER Classic project file /project/4kze/vhdl/gpio.lci --> preference file /project/4kze/vhdl/gpio_test_vhdaf.udo --> script for VHDL functional simulation with Active HDL /project/4kze/vhdl/gpio_test_vhda.udo --> script for VHDL timing simulation with Active HDL /project/xo/verilog/gpio.syn --> ispLEVER project file /project/xo/verilog/gpio.lpf --> preference file /project/xo/verilog/gpio_test_tff.udo --> script for Verilog functional simulation with Active HDL /project/xo/verilog/gpio_test_tfr.udo --> script for Verilog post route functional simulation with Active HDL /project/xo/verilog/gpio_test_tf.udo --> script for Verilog timing simulation with Active HDL /project/xo/vhdl/gpio.syn --> ispLEVER project file /project/xo/vhdl/gpio.lpf --> preference file /project/xo/vhdl/gpio_test_vhdf.udo --> script for VHDL functional simulation with Active HDL /project/xo/vhdl/gpio_test_vhdr.udo --> script for VHDL post route functional simulation with Active HDL /project/xo/vhdl/gpio_test_vhd.udo --> script for VHDL timing simulation with Active HDL /project/xp2/verilog/gpio.syn --> ispLEVER project file /project/xp2/verilog/gpio.lpf --> preference file /project/xp2/verilog/gpio_test_tff.udo --> script for Verilog functional simulation with Active HDL /project/xp2/verilog/gpio_test_tfr.udo --> script for Verilog post route functional simulation with Active HDL /project/xp2/verilog/gpio_test_tf.udo --> script for Verilog timing simulation with Active HDL /project/xp2/vhdl/gpio.syn --> ispLEVER project file /project/xp2/vhdl/gpio.lpf --> preference file /project/xp2/vhdl/gpio_test_vhdf.udo --> script for VHDL functional simulation with Active HDL /project/xp2/vhdl/gpio_test_vhdr.udo --> script for VHDL post route functional simulation with Active HDL /project/xp2/vhdl/gpio_test_vhd.udo --> script for VHDL timing simulation with Active HDL 3. /source/verilog/gpio_top.v --> source file - top level /source/verilog/bank_func.v --> source file /source/vhdl/gpio_top.vhd --> source file - top level /source/vhdl/bank_func.vhd --> source file 4. /testbench/verilog/gpio_test.v --> Testbench/models for simulation /testbench/vhdl/gpio_test.vhd --> Testbench for simulation /testbench/vhdl/spi_slave.vhd --> SPI slave model for simulation How to bring up the project: 1. Unzip the RD1065_revyy.y.zip file using the existing folder names, where yy.y is the current version of the zip file 2. Run ispLEVER Classic Project Navigator for 4kze projects, run ispLEVER Project Navigator for xo/xp2 projects; 3. In the File menu, click on Open Project, then browse to the directory where the reference design is placed, select RD1065\project\\verilog(vhdl)\gpio.syn and click Open... Running simulation for 4kze projects 1. Open the project with ispLEVER Classic Project Navigator as above 2. In ispLEVER Project Navigator, highlight the ..\..\..\testbench\verilog(vhdl)\gpio_test.v(vhd) file on the left-side panel, user will see 2 simulation options on the right panel. 3. For functional simulation, double click on 'Aldec Verilog(VHDL) Functional Simulation', the Aldec simulator will be brought up. If prompted, click yes to overwrite the existing file. 4. Functional simulation will run until complete. user will see a script shown in the Console panel like this: # KERNEL: 0 ns : Reset process # KERNEL: 500 ns : Reset done # KERNEL: 525 ns : cpu select bank 0, start to write test data 0x00 to interrupt mask register # KERNEL: 625 ns : cpu select bank 0, start to initialize interrupt mask register with 0x0F # KERNEL: 725 ns : cpu select bank 0, start to write test data 0x0A to interrupt polarity register # KERNEL: 825 ns : cpu select bank 0, start to initialize interrupt polarity register with 0x00 # KERNEL: 925 ns : cpu select bank 0, start to write test data 0x0F to bank data output register # KERNEL: 1025 ns : cpu select bank 0, start to write test data 0x01 to data enable register # KERNEL: 1125 ns : cpu select bank 0, start to initialize data enable register with 0x0E # KERNEL: 1225 ns : cpu select bank 0, start to write test data 0x07 to bank data output register # KERNEL: 1325 ns : cpu select bank 0, start to initialize bank data output register with 0x00 # KERNEL: 1575 ns : cpu select bank 0, start to read data from interrupt mask register # KERNEL: 1675 ns : cpu select bank 0, start to read data from interrupt polarity register # KERNEL: 1775 ns : cpu select bank 0, start to read data from data enable register # KERNEL: 1875 ns : cpu select bank 0, start to read data from bank data output register # KERNEL: 2125 ns : Generate spi timing, SCLK 1 # KERNEL: 2277 ns : mosi_slave= 1 # KERNEL: 2277 ns : SPI slave model will send out 01010101 to miso_master(MSB first) # KERNEL: 2425 ns : miso_master= 0 # KERNEL: 2475 ns : Generate spi timing, SCLK 2 # KERNEL: 2627 ns : mosi_slave= 0 # KERNEL: 2775 ns : miso_master= 1 # KERNEL: 2825 ns : Generate spi timing, SCLK 3 # KERNEL: 2977 ns : mosi_slave= 1 # KERNEL: 3125 ns : miso_master= 0 # KERNEL: 3175 ns : Generate spi timing, SCLK 4 # KERNEL: 3327 ns : mosi_slave= 0 # KERNEL: 3475 ns : miso_master= 1 # KERNEL: 3525 ns : Generate spi timing, SCLK 5 # KERNEL: 3677 ns : mosi_slave= 1 # KERNEL: 3825 ns : miso_master= 0 # KERNEL: 3875 ns : Generate spi timing, SCLK 6 # KERNEL: 4027 ns : mosi_slave= 0 # KERNEL: 4175 ns : miso_master= 1 # KERNEL: 4225 ns : Generate spi timing, SCLK 7 # KERNEL: 4377 ns : mosi_slave= 1 # KERNEL: 4525 ns : miso_master= 0 # KERNEL: 4575 ns : Generate spi timing, SCLK 8 # KERNEL: 4727 ns : mosi_slave= 0 # KERNEL: 4875 ns : miso_master= 1 # KERNEL: stopped at time: 5 us 5. For timing simulation, double click on 'Aldec Verilog(VHDL) Timing Simulation'. Similar message will be shown in the console panel of the Aldec Active-HDL simulator. Running simulation for the xo/xp2 projects 1. Open the project with ispLEVER Project Navigator 2. In ispLEVER Project Navigator, highlight the ..\..\..\testbench\verilog(vhdl)\gpio_test.v(vhd) file on the left-side panel, user will see 3 simulation options on the right panel. 3. For functional simulation, double click on 'Verilog(VHDL) Functional Simulation with Aldec Active-HDL', Aldec simulator will be brought up. If prompted, click yes to overwrite the existing file. The simulation will run until complete. 4. For post route functional simulation, double click 'Verilog(VHDL) Post Route Functional Simulation with Aldec Active-HDL' to start the simulator as above. 5. For timing simulation, double-click 'Verilog(VHDL) Post Route Timing Simulation with Aldec Active-HDL' and start the simulator. How to run Place and Route, JEDEC generation, and Timing Analysis: 1. Highlight the device on the left-side panel of the Project Navigator. On the right-side panel, double click on Place and Route Design or Fit Design in ispLEVER Classic. This will bring the design through synthesis, mapping, and place and route. 2. Highlight the device on the left-side panel of the Project Navigator. On the right-side panel, double click on Generate Data File (JEDEC file in ispLEVER Classic). This will generate the jedec file for the design. 3. Once Place and Route is done, user can double click on Place and Route Trace Report (or Timing Report in ispLEVER Classic) on the right-side panel to get the timing analysis result.

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