nios_dds
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：3041KB
下载次数：35
上传日期：2010-11-23 16:55:59
上 传 者：
Tomy Lee
说明： 采用Altera的NIOS内核，配合独立的累加器，实现了正弦波，三角波，锯齿波和方波的DDS产生电路，系统时钟最高可达120MHz，配合高速DAC，可产生最高约40MHz左右的波形
(Using Altera' s NIOS core, with a separate accumulator, to achieve a sine wave, triangle wave, sawtooth and square wave generation circuit DDS system clock up to 120MHz, with high-speed DAC, can produce up to about 40MHz waveform around)
文件列表:
nios_dds\.sopc_builder\.svn\all-wcprops (446, 2010-11-19)
nios_dds\.sopc_builder\.svn\entries (645, 2010-11-19)
nios_dds\.sopc_builder\.svn\text-base\install.ptf.svn-base (13818, 2010-11-18)
nios_dds\.sopc_builder\.svn\text-base\install2.ptf.svn-base (8794, 2010-11-19)
nios_dds\.sopc_builder\.svn\text-base\preferences.xml.svn-base (771, 2010-11-19)
nios_dds\.sopc_builder\install.ptf (13818, 2010-11-19)
nios_dds\.sopc_builder\install2.ptf (8794, 2010-11-19)
nios_dds\.sopc_builder\preferences.xml (771, 2010-11-19)
nios_dds\.svn\all-wcprops (16824, 2010-11-19)
nios_dds\.svn\entries (24221, 2010-11-19)
nios_dds\.svn\prop-base\acc_wave0.jpg.svn-base (53, 2010-11-19)
nios_dds\.svn\prop-base\bin2hex.com.svn-base (53, 2010-11-19)
nios_dds\.svn\prop-base\cpu.ocp.svn-base (53, 2010-11-18)
nios_dds\.svn\prop-base\cpu.v.svn-base (53, 2010-11-18)
nios_dds\.svn\prop-base\EP2C8_EVK_0A1.pdf.svn-base (53, 2010-11-18)
nios_dds\.svn\prop-base\lpm_rom0_wave0.jpg.svn-base (53, 2010-11-19)
nios_dds\.svn\prop-base\nios_sys.pof.svn-base (53, 2010-11-18)
nios_dds\.svn\prop-base\nios_sys.sof.svn-base (53, 2010-11-18)
nios_dds\.svn\prop-base\saw.bin.svn-base (53, 2010-11-19)
nios_dds\.svn\prop-base\saw_rom_wave0.jpg.svn-base (53, 2010-11-19)
nios_dds\.svn\prop-base\sine.bin.svn-base (53, 2010-11-19)
nios_dds\.svn\prop-base\squ.bin.svn-base (53, 2010-11-19)
nios_dds\.svn\prop-base\squ_rom_wave0.jpg.svn-base (53, 2010-11-19)
nios_dds\.svn\prop-base\tri.bin.svn-base (53, 2010-11-19)
nios_dds\.svn\prop-base\tri_rom_wave0.jpg.svn-base (53, 2010-11-19)
nios_dds\.svn\text-base\7404_0.vhd.svn-base (1190, 2010-11-19)
nios_dds\.svn\text-base\7404_1.vhd.svn-base (1190, 2010-11-19)
nios_dds\.svn\text-base\7404_3.vhd.svn-base (1190, 2010-11-19)
nios_dds\.svn\text-base\7404_4.vhd.svn-base (1189, 2010-11-19)
nios_dds\.svn\text-base\7404_5.vhd.svn-base (1189, 2010-11-19)
nios_dds\.svn\text-base\7404_6.vhd.svn-base (1189, 2010-11-19)
nios_dds\.svn\text-base\74139m_2.vhd.svn-base (1390, 2010-11-19)
nios_dds\.svn\text-base\acc.bsf.svn-base (3073, 2010-11-19)
nios_dds\.svn\text-base\acc.cmp.svn-base (1039, 2010-11-19)
nios_dds\.svn\text-base\acc.qip.svn-base (355, 2010-11-19)
nios_dds\.svn\text-base\acc.vhd.svn-base (4807, 2010-11-19)
nios_dds\.svn\text-base\acc_wave0.jpg.svn-base (86183, 2010-11-19)
nios_dds\.svn\text-base\acc_waveforms.html.svn-base (569, 2010-11-19)
nios_dds\.svn\text-base\altpllsys_pll.bsf.svn-base (2996, 2010-11-18)
nios_dds\.svn\text-base\altpllsys_pll.cmp.svn-base (913, 2010-11-18)
... ...
使用说明:
1.用quartus打开nios_sys.qpf,将nios_sys.sof写入FPGA
2.运行SOPC builder,打开core.sopc,选择system generation页,点击NIOS IDE运行NIOS软件开发环境
3.在hello工程上右键选择run as NIOS II hardware即可将程序编译并下载到FPGA中运行
4.如果要将程序写入flash,则从tools菜单打开flash programmer,在additionalnios2-flash-programmer arguments:输入--instance=0,在Additional sof2flash arguments:输入--override=29lv800_override.txt,然后点击下方的program flash按钮
或者是通过NIOS command shell命令行工具,进入\software\memtest\Debug\目录,然后用命令nios2-flash-programmer -b 0x0 --override=29lv800_override.txt ext_flash.flash对flash进行编程
已知问题:
1.SRAM的测试地址.原来设计时准备采用32KB的芯片,但是因为公司已有芯片为W2465(8KB),而W2465的26pin为CS信号,所以在测试W2465时需要将A13设为高才能正常读写,也就是必须将SRAM的base address+0x2000作为W2465的base address.而如果焊接的是IS62LV256则没有这个问题.
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