source
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：9KB
下载次数：8
上传日期：2010-11-24 23:38:12
上 传 者：
123_abz
说明： 本源码是 基于VERILOG的SDRAM的开发与实现
并能实现 刷新，预充电，突发长度为8字节等功能 已验证，可用
(The source is based on the SDRAM VERILOG development and implementation and to achieve refresh, precharge, a burst length of 8 bytes and other functions have been verified, the available)
文件列表:
source\para.v (565, 2010-09-14)
source\pll.v (18238, 2010-09-13)
source\sdram_cmd.v (6750, 2010-09-08)
source\sdram_ctrl_top.v (2271, 2010-09-08)
source\sdram_ctrl_top_test.v (1685, 2010-09-13)
source\sdram_data_path.v (1307, 2010-09-09)
source\sdram_state_ctrl.v (12467, 2010-09-09)
source\sys_clk_ctrl.v (2318, 2010-09-14)
source (0, 2010-11-24)
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