Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Ex
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：285KB
下载次数：32
上传日期：2010-11-30 14:47:36
上 传 者：
hasea
说明： 来自于ALTERA官方网站。
本文档详细介绍怎样利用MAX® II CPLD 来实现脉冲宽度调制(PWM)。本设计还利用了MAX II CPLD 的内部用户闪存振荡器，不需要采用专门的外部时钟。
附有verilog源程序。
(From ALTERA website. This document details how to use the MAX ® II CPLD to implement pulse width modulation (PWM). This design also uses the MAX II CPLD' s internal oscillator user flash memory, without using a special external clock. With verilog source.)
文件列表:
利用MAX II CPLD 实现 脉冲宽度调制.pdf (222947, 2010-11-08)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\code\pwm_main.v (4664, 2006-12-27)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\pulse_width_modulator.cr.mti (1066, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\pulse_width_modulator.mpf (17172, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\pwm_main.v (4664, 2006-12-27)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\pwm_sim.cr.mti (938, 2006-12-29)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\pwm_sim.mpf (9993, 2006-12-29)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\test_pwm.v (8158, 2006-12-28)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave.bmp (248182, 2006-12-29)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave.do (1804, 2006-12-29)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave2.bmp (248182, 2006-12-29)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave2.do (1618, 2006-12-29)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave3.bmp (248182, 2006-12-29)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave3.do (1617, 2006-12-29)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave4.bmp (248182, 2006-12-29)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave4.do (1619, 2006-12-29)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave5.bmp (248182, 2006-12-29)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave5.do (1619, 2006-12-29)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\altufm_osc0_altufm_osc_1p3\verilog.asm (6531, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\altufm_osc0_altufm_osc_1p3\_primary.dat (850, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\altufm_osc0_altufm_osc_1p3\_primary.vhd (214, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clkgen\verilog.asm (3779, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clkgen\_primary.dat (341, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clkgen\_primary.vhd (217, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clk_gen\verilog.asm (3827, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clk_gen\_primary.dat (362, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clk_gen\_primary.vhd (219, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\dutycycle\verilog.asm (3674, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\dutycycle\_primary.dat (416, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\dutycycle\_primary.vhd (285, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\duty_cycle\verilog.asm (3649, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\duty_cycle\_primary.dat (420, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\duty_cycle\_primary.vhd (287, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\pwm_gen\verilog.asm (4431, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\pwm_gen\_primary.dat (524, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\pwm_gen\_primary.vhd (238, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\pwm_main\verilog.asm (6096, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\pwm_main\_primary.dat (736, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\pwm_main\_primary.vhd (436, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\test_pwm\verilog.asm (28202, 2007-11-05)
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