文件列表:

adder_fa4bit\bench\adder_4bit_tb.v (2830, 2002-10-01)
adder_fa4bit\bench\adder_4bit_tb.v.bak (2876, 2009-02-02)
adder_fa4bit\bench (0, 2002-10-01)
adder_fa4bit\rtl\fulladder_1bit.v (2827, 2002-10-01)
adder_fa4bit\rtl\fulladder_1bit.v.bak (2827, 2002-10-01)
adder_fa4bit\rtl\fulladder_4bit.v (3984, 2002-10-01)
adder_fa4bit\rtl\fulladder_4bit.v.bak (4032, 2009-02-02)
adder_fa4bit\rtl\halfadder_1bit.v (2449, 2002-10-01)
adder_fa4bit\rtl\halfadder_1bit.v.bak (2491, 2009-02-02)
adder_fa4bit\rtl (0, 2002-10-01)
adder_fa4bit\sim\adder4bit_by_1bit.cr.mti (1505, 2008-06-09)
adder_fa4bit\sim\adder4bit_by_1bit.mpf (14356, 2008-06-09)
adder_fa4bit\sim\vsim.wlf (16384, 2006-01-31)
adder_fa4bit\sim\wave.do (1019, 2006-01-31)
adder_fa4bit\sim\work\adder_4bit_tb\verilog.asm (9426, 2008-06-09)
adder_fa4bit\sim\work\adder_4bit_tb\_primary.dat (1101, 2008-06-09)
adder_fa4bit\sim\work\adder_4bit_tb\_primary.vhd (86, 2008-06-09)
adder_fa4bit\sim\work\adder_4bit_tb (0, 2010-07-03)
adder_fa4bit\sim\work\fulladder_1bit\verilog.asm (3671, 2008-06-09)
adder_fa4bit\sim\work\fulladder_1bit\_primary.dat (509, 2008-06-09)
adder_fa4bit\sim\work\fulladder_1bit\_primary.vhd (319, 2008-06-09)
adder_fa4bit\sim\work\fulladder_1bit (0, 2010-07-03)
adder_fa4bit\sim\work\fulladder_4bit\verilog.asm (5009, 2008-06-09)
adder_fa4bit\sim\work\fulladder_4bit\_primary.dat (934, 2008-06-09)
adder_fa4bit\sim\work\fulladder_4bit\_primary.vhd (376, 2008-06-09)
adder_fa4bit\sim\work\fulladder_4bit (0, 2010-07-03)
adder_fa4bit\sim\work\halfadder_1bit\verilog.asm (2391, 2008-06-09)
adder_fa4bit\sim\work\halfadder_1bit\_primary.dat (253, 2008-06-09)
adder_fa4bit\sim\work\halfadder_1bit\_primary.vhd (276, 2008-06-09)
adder_fa4bit\sim\work\halfadder_1bit (0, 2010-07-03)
adder_fa4bit\sim\work\_info (1258, 2008-06-09)
adder_fa4bit\sim\work (0, 2010-07-03)
adder_fa4bit\sim (0, 2010-07-03)
adder_fa4bit (0, 2010-07-03)

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