文件列表:

8b10b_Decoder (0, 2000-07-11)
8b10b_Decoder\8b10b_Decoder.npl (1160, 2000-04-04)
8b10b_Decoder\decoder.ucf (55, 2000-04-04)
8b10b_Decoder\dec_func.vhd (10575, 2000-03-31)
8b10b_Decoder\err_check.vhd (4991, 2000-03-31)
8b10b_Decoder\main_dec.vhd (8478, 2000-04-04)
8b10b_Decoder\time_sim_dec.vho (53410, 2000-04-04)
8b10b_Decoder\work (0, 2000-07-11)
8b10b_Decoder\work\vhdllib.ref (449, 2000-04-04)
8b10b_Decoder\work\VHPL0.vho (3025, 2000-04-04)
8b10b_Decoder\work\VHPL0.vhr (75, 2000-04-04)
8b10b_Decoder\work\VHPL1.vho (47964, 2000-04-04)
8b10b_Decoder\work\VHPL1.vhr (128, 2000-04-04)
8b10b_Decoder\work\VHPL2.vho (2137, 2000-04-04)
8b10b_Decoder\work\VHPL2.vhr (77, 2000-04-04)
8b10b_Decoder\work\VHPL3.vho (13144, 2000-04-04)
8b10b_Decoder\work\VHPL3.vhr (131, 2000-04-04)
8b10b_Decoder\work\VHPL4.vho (1540, 2000-04-04)
8b10b_Decoder\work\VHPL4.vhr (94, 2000-04-04)
8b10b_Decoder\work\VHPL5.vho (15137, 2000-04-04)
8b10b_Decoder\work\VHPL5.vhr (125, 2000-04-04)
8b10b_Decoder\_top.ucf (55, 2000-04-04)
8b10b_Encoder (0, 2000-07-11)
8b10b_Encoder\8b10b.npl (1832, 2000-07-11)
8b10b_Encoder\dec_func.vhd (10575, 2000-03-31)
8b10b_Encoder\dis_gen.vhd (6134, 2000-04-04)
8b10b_Encoder\enc_dec.do (50, 2000-04-04)
8b10b_Encoder\enc_func.vhd (8327, 2000-07-11)
8b10b_Encoder\err_check.vhd (4991, 2000-03-31)
8b10b_Encoder\main_dec.vhd (8478, 2000-04-04)
8b10b_Encoder\main_enc.vhd (11012, 2000-07-11)
8b10b_Encoder\main_tb.vhd (5112, 2000-04-04)
8b10b_Encoder\main_tb._vfd (337, 2000-07-11)
8b10b_Encoder\pkg_convert.vhd (2156, 2000-04-04)
8b10b_Encoder\pkg_spc_char.vhd (1827, 2000-04-04)
8b10b_Encoder\s_gen.vhd (4330, 2000-03-31)
8b10b_Encoder\tst_bench.vhd (10034, 2000-07-11)
8b10b_Encoder\wave.do (2642, 2000-04-04)
8b10b_Encoder\work (0, 2000-07-11)
8b10b_Encoder\work\decoder (0, 2000-07-11)
... ...

******************************************************************************************************************************************** README File for 8B/10B Encoder/Decoder Customer Pack Created: 7-11-2000 Jennifer Jenkins ******************************************************************************************************************************************** ******************************************************************************************************************************************** DISCLAIMER ******************************************************************************************************************************************** THIS DESIGN IS PROVIDED TO YOU “AS IS”. XILINX MAKES AND YOU RECEIVE NO WARRANTIES OR CONDITIONS, EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, AND XILINX SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR A PARTICULAR PURPOSE. This design has not been verified on hardware (as opposed to simulations), and it should be used only as an example design, not as a fully functional core. XILINX does not warrant the performance, functionality, or operation of this Design will meet your requirements, or that the operation of the Design will be uninterrupted or error free, or that defects in the Design will be corrected. Furthermore, XILINX does not warrant or make any representations regarding use or the results of the use of the Design in terms of correctness, accuracy, reliability or otherwise. ******************************************************************************************************************************************** FILE CONTENTS ******************************************************************************************************************************************** This zip file contains the following: Folders: \8b10b_Encoder -- Encoder VHDL files and Proj Nav. project file \work -- XST and ModelSim compiled VHDL files -- Note: This directory should be used for simulation of both the encoder and decoder logic \8b10b_Decoder -- Decoder VHDL files and Proj Nav. project file \work -- XST and ModelSim compiled VHDL files VHDL Source Files: ---------------------------------------- 8B10B ENCODER --------------------------------------------- main_enc.vhd (entity: ENCODER) -- Main upper encoder control logic. Instantiates ENC_FUNC, DIS_GEN_UP, COMP_GEN, and S_GEN modules. enc_func.vhd (entity: ENC_FUNC) -- Main 8B/10B encoder logic. Controls generation of encoded output data. Receives output signals from DIS_GEN_UP, COMP_GEN, and S_GEN modules. Includes disparity functions, complement functions, and sout. dis_gen.vhd (entity: DIS_GEN) -- Generates running disparity functions (nds4, pds4, nds6, and pds6) and disparity out (dis_out) for 8B/10B module. s_gen.vhd (entity: S_GEN) -- Generates the S signal used in 8B/10B encoding scheme (fout and jout). -------------------------------------------- 8B10B DECODER ------------------------------------------- main_dec.vhd (entity: DECODER) -- Main 10B/8B decoder control logic. Instantiates DEC_FUNC, ERR_CHK modules. dec_func.vhd (entity: DEC_FUNC) -- Main 10B/8B decoder logic. Controls generation of decoding serial input data to 8-bit data output. err_chk.vhd (entity: ERR_CHK) -- Detects errors in data sent for each 10B/8B decoding module. Asserts err_out accordingly. VHDL Testbench Files: main_tb.vhd (entity: MAIN_TB) -- Top-level test module for functional simulation. Instantiates encoder (ENCODER), decoder (DECODER), and test bench (TST_BENCH). tst_bench.vhd (entity: TST_BENCH) -- Functional simulation test bench. Sends data to encoder, monitors control, and reads data from decoder. Tests 100 data bit patterns and all special character transmission. pkg_convert.vhd -- Describes functions for converting integers and 8-bit vectors (INT2VEC and VEC2INT). pkg_spec_char.vhd -- Describes function SPEC_CHAR which generates special characters for testing. ModelSim DO files: enc_dec.do -- Functional simulation script file that calls wave.do wave.do -- Configures Modelsim wave window for functional simulation. ******************************************************************************************************************************************** TESTING NOTES ******************************************************************************************************************************************** Each 8B/10B encoder and decoder design is available seperately to the user upon downloading. Both designs must be utilized for testing function simulations with the provided test benches. Note each encoder and decoder has separate project files for use in Project Navigator. These modules were seperated for compilation and fitting into a specific CPLD. When utilizing the functionality of test benches in Project Navigator, ModelSim is used for simulation purposes. Note all the above test benches are included in the encoder project heirarchy. For this reason, the decoder design files are duplicated in the encoder project for use when using ModelSim for simulation purposes. Upon invoking ModelSim with the test benches provided for function simulation, the encoder, decoder and test bench modules will be loaded as the current design. The decoder design files as described below are loaded with the encoder project to run the test benches. Simulation Type Imported files Functional: main_dec.vhd dec_func.vhd err_chk.vhd Post-Route: time_sim_dec.vhd Note: If any changes are made to any of the above decoder files within the encoder project directory, they must be recompiled and loaded in ModelSim. When starting ModelSim, make sure the vsim DO file is specified, enc_dec.do for functional simulation. At this point the wave.do file will be used accordingly. The test bench environment is described and documented in XAPP336 (Designing for 16B/20B Encoding/Decoding Applications) available for download on the Xilinx web site (www.xilinx.com). ******************************************************************************************************************************************** DESIGN NOTES ******************************************************************************************************************************************** This 8B/10B encoder and decoder design was done according to 8B/10B encoding and decoding specification. The control model used for this design may require modification for a specific application. Complete documentation for the design can be found in XAPP336 (Designing for 16B/20B Encoding/Decoding Applications) available for download from the Xilinx web site (www.xilinx.com). All of the control signals are defined in the VHDL source files and can be easily customized for customer use. For both the encoder and decoder modules the handshaking signals, FRAME_IN and FRAME_OUT are identical and can be modified for a specific application. For the test bench created with this design, the handshaking of data to and from each module is done with these signals, FRAME_IN and FRAME_OUT. The running disparity controlled in this design is also monitored in the test bench VHDL description. The disparity out of one 16-bit data transmission is kept and implemented as the disparity into the next transmitted data. Remember this is implemented in the test bench and can be modified for customer use. Note the data out of each encoder and decoder module is registered based on each VHDL state machine transition. The test bench in this design captures the output data of the encoder and it is kept and used as the input to the decoder at the time specific. Again this was implemented in the specific test bench with this design and can be easily modified. Each 8B/10B encoder and decoder design has been targeted separately to a XCR30***-10VQ44C CoolRunner CPLD. This is a 3V, *** macrocell device in a 44VQFP package. The fitter was designated to select the pin-out for the device. Please also note that this design has been verified through simulations, and not on actual hardware. ******************************************************************************************************************************************** Technical Support ******************************************************************************************************************************************** Technical support for this design and any other CoolRunner CPLD issues can be obtained as follows: North American Support (Mon,Tues,Wed,Fri 6:30am-5pm Thr 6:30am - 4:00pm Pacific Standard Time) Hotline: 1-800-255-7778 or (408) 879-5199 Fax: (408) 879-4442 Email: hotline@xilinx.com United Kingdom Support (Mon,Tues,Wed,Thr 9:00am-12:00pm, 1:00-5:30pm Fri 9:00am-12:00pm, 1:00-3:30pm) Hotline: +44 1932 820821 Fax: +44 1932 828522 Email : ukhelp@xilinx.com France Support (Mon,Tues,Wed,Thr,Fri 9:30am-12:30pm, 2:00-5:30pm) Hotline: +33 1 3463 0100 Fax: +33 1 3463 0959 Email : frhelp@xilinx.com Germany Support (Mon,Tues,Wed,Thr 8:00am-12:00pm, 1:00-5:00pm, Fri 8:00am-12:00pm, 1:00pm-3:00pm) Hotline: +49 89 991 54930 Fax: +49 89 904 4748 Email : dlhelp@xilinx.com Japan Support (Mon,Tues,Thu,Fri 9:00am -5:00pm () Wed 9:00am -4:00pm) Hotline: (81)3-3297-9163 Fax:: (81)3-3297-0067 Email: jhotline@xilinx.com

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