xapp353

所属分类:VHDL/FPGA/Verilog
开发工具:Unix_Linux
文件大小:1063KB
下载次数:22
上传日期:2005-12-31 15:18:49
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说明:  可编程器件厂商Xilinx的用于设计SMBus 控制器的源程序,包括完整的说明帮助,以及可以用于xlinx器件的可综合的代码
(makers Xilinx programmable devices used in the design of the controller SMBus source, including a complete explanation of help and can be used xlinx devices can be integrated code)

文件列表:
micro_tb.vhd (23078, 2001-01-08)
micro_test.do (1167, 2001-11-09)
micro_test.vhd (4459, 2001-01-08)
micro_test_post.do (549, 2001-11-09)
pullup.vhd (243, 2000-02-02)
read_me.doc (27648, 2002-02-15)
shift.vhd (1724, 2000-06-14)
smbus.npl (1229, 2001-11-16)
smbus.vhd (9830, 2001-01-05)
smbus_control.vhd (37722, 2002-02-15)
smbus_timesim.vhd (520380, 2002-02-15)
uc_interface.vhd (11997, 2001-01-05)
upcnt21.vhd (1577, 2001-01-05)
upcnt4.vhd (1465, 2000-03-16)
upcnt9.vhd (1509, 2000-06-14)
wave.do (1820, 2001-01-11)
wave_post.do (2959, 2002-02-15)
work (0, 2002-02-15)
work\micro_tb (0, 2002-02-15)
work\micro_tb\rtl.dat (9419, 2002-02-15)
work\micro_tb\rtl.psm (45104, 2002-02-15)
work\micro_tb\_primary.dat (579, 2002-02-15)
work\micro_test (0, 2002-02-15)
work\micro_test\archmicro_test.dat (1870, 2002-02-15)
work\micro_test\archmicro_test.psm (8000, 2002-02-15)
work\micro_test\_primary.dat (110, 2002-02-15)
work\pullup (0, 2002-02-15)
work\pullup\archpullup.dat (104, 2002-02-15)
work\pullup\archpullup.psm (576, 2002-02-15)
work\pullup\_primary.dat (175, 2002-02-15)
work\roc (0, 2002-02-15)
work\roc\roc_v.dat (317, 2002-02-15)
work\roc\roc_v.psm (2056, 2002-02-15)
work\roc\_primary.dat (295, 2002-02-15)
work\shift8 (0, 2002-02-15)
work\shift8\definition.dat (521, 2002-02-15)
work\shift8\definition.psm (3808, 2002-02-15)
work\shift8\_primary.dat (402, 2002-02-15)
work\smbus (0, 2002-02-15)
... ...

************************************************************************* Readme File for SMBus Customer Pack Created: 1/11/01 JRH ************************************************************************* ************************************************************************* DISCLAIMER ************************************************************************* THIS DESIGN IS PROVIDED TO YOU “AS IS”. XILINX MAKES AND YOU RECEIVE NO WARRANTIES OR CONDITIONS, EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, AND XILINX SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR A PARTICULAR PURPOSE. This design has not been verified on hardware (as opposed to simulations), and it should be used only as an example design, not as a fully functional core. XILINX does not warrant the performance, functionality, or operation of this Design will meet your requirements, or that the operation of the Design will be uninterrupted or error free, or that defects in the Design will be corrected. Furthermore, XILINX does not warrant or make any representations regarding use or the results of the use of the Design in terms of correctness, accuracy, reliability or otherwise. ************************************************************************* File Contents ************************************************************************* This zip file contains the following folders: \work -- XST and ModelSim compiled VHDL files -- VHDL Source Files: smbus.vhd - top level file smbus_control.vhd - control function for the SMBus master/slave uc_interface.vhd - uC interface function for a Hitachi SH7750-like uC shift.vhd - shift register upcnt4.vhd - 4-bit up counter upcnt9.vhd - 9-bit up counter upcnt21.vhd - 21-bit up counter smbus_timesim.vhd - XST compiled version of smbus.vhd, smbus_control.vhd, and uc_interface.vhd which contains the timing delay data for the XCR3256XL-7TQ144 device to which this SMBus design was targeted. --VHDL Testbench Files: micro_test.vhd -- top-level VHDL testbench for simulation that instantiates micro_tb.vhd, pullup.vhd, and smbus.vhd. micro_tb.vhd -- VHDL simulation testbench that tests two instantiations of the SMBus design. It configures one as a master and one as a slave and then the two SMBus designs transfer data over SMBus. pullup.vhd -- models a pull-up resistor -- ModelSim DO files: micro_test.do -- functional simulation script file that compiles smbus.vhd, smbus_control.vhd, uc_interface.vhd, shift.vhd, upcnt4.vhd, upcnt9.vhd, ucnt21.vhd, micro_test.vhd, micro_tb.vhd, and pullup.vhd. Then loads the design micro_test and calls wave.do wave.do -- configures wave window for functional simulation micro_test_post.do -- post-route simulation script file that compiles time_sim.vhd, micro_test_post.vhd, micro_tb.vhd, and pullup.vhd. Then loads the design micro_test_post and calls wave_post.do wave_post.do -- configures wave window for post-route simulation ************************************************************************* Design Notes ************************************************************************* The SMBus design was designed using the timing diagrams in Section 23.3.3 - BUS TIMING of the specification for the Hitachi SH7750 uC. Complete documentation for the design can be found in XAPP353 available for download from the Xilinx website. All of the register addresses are defined as constants in the VHDL source files and can be easily customized for customer use. The MBASE address is defined as a generic and can also be easily changed and customized for customer use. In addition, this design outputs the MCF signal on a pin which can be used by the uC as a quick indication that the SMBus transfer is complete. This design is targeted to the XCR3256XL-7TQ144C CoolRunner CPLD. This is a 3V, 256 macrocell device in a 144TQFP package. The fitter was allowed to pick the pin-out for the device. IMPORTANT NOTE: This design uses the SMBus SCL signal as a clock. This requires that the SCL signal have clean, fast edges on both the rising and falling edges of this signal. Slow rise and fall times on this signal can show noise effects which can cause improper clocking of registers within the CoolRunner CPLD. If the loading of the SCL signal in the system is such that the rise and fall times are slow (>100nS), this signal will need to be buffered external to the CPLD. Please also note that this design has been verified through simulations, but not on actual hardware. ************************************************************************* Technical Support ************************************************************************* Technical support for this design and any other CoolRunner CPLD issues can be obtained as follows: North American Support (Mon,Tues,Wed,Fri 6:30am-5pm Thr 6:30am - 4:00pm Pacific Standard Time) Hotline: 1-800-255-7778 or (408) 879-5199 Fax: (408) 879-4442 Email: hotline@xilinx.com United Kingdom Support (Mon,Tues,Wed,Thr 9:00am-12:00pm, 1:00-5:30pm Fri 9:00am-12:00pm, 1:00-3:30pm) Hotline: +44 1932 820821 Fax: +44 1932 828522 Email : ukhelp@xilinx.com France Support (Mon,Tues,Wed,Thr,Fri 9:30am-12:30pm, 2:00-5:30pm) Hotline: +33 1 3463 0100 Fax: +33 1 3463 0959 Email : frhelp@xilinx.com Germany Support (Mon,Tues,Wed,Thr 8:00am-12:00pm, 1:00-5:00pm, Fri 8:00am-12:00pm, 1:00pm-3:00pm) Hotline: +49 89 991 54930 Fax: +49 89 904 4748 Email : dlhelp@xilinx.com Japan Support (Mon,Tues,Thu,Fri 9:00am -5:00pm () Wed 9:00am -4:00pm) Hotline: (81)3-3297-9163 Fax:: (81)3-3297-0067 Email: jhotline@xilinx.com

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