mi2c
所属分类:VHDL/FPGA/Verilog
开发工具:Windows_Unix
文件大小:1505KB
下载次数:31
上传日期:2006-01-02 11:52:08
上 传 者:
joe_ma
说明: altera i2c host/device
(ALTERA i2c host/device)
文件列表:
mi2c\docs\mi2c_pd.pdf (35888, 2001-10-02)
mi2c\docs\mi2c_ps.pdf (91216, 2001-10-02)
mi2c\docs (0, 2005-11-22)
mi2c\verilog\gate_sim\comp_altera_lib.do (641, 2001-10-02)
mi2c\verilog\gate_sim\comp_gate.do (1087, 2001-10-02)
mi2c\verilog\gate_sim\mi2c_tb.bat (42, 2001-10-02)
mi2c\verilog\gate_sim\mi2c_tb.do (1062, 2001-10-02)
mi2c\verilog\gate_sim\mi2c_tb.ref (4689832, 2001-10-02)
mi2c\verilog\gate_sim\mi2c_tb.scr (55, 2001-10-02)
mi2c\verilog\gate_sim\mi2c_tb_diff.bat (48, 2001-10-02)
mi2c\verilog\gate_sim\mi2c_tb_diff.scr (64, 2001-10-02)
mi2c\verilog\gate_sim\work\mi2c_tb\verilog.asm (591028, 2001-10-02)
mi2c\verilog\gate_sim\work\mi2c_tb\_primary.dat (87980, 2001-10-02)
mi2c\verilog\gate_sim\work\mi2c_tb\_primary.vhd (74, 2001-10-02)
mi2c\verilog\gate_sim\work\mi2c_tb (0, 2005-11-22)
mi2c\verilog\gate_sim\work\_info (202, 2001-10-02)
mi2c\verilog\gate_sim\work (0, 2005-11-22)
mi2c\verilog\gate_sim (0, 2005-11-22)
mi2c\verilog\rtl_encrypted\m3s001br.v (4223, 2005-11-22)
mi2c\verilog\rtl_encrypted\m3s001br.v.old (4262, 2001-10-02)
mi2c\verilog\rtl_encrypted\m3s002br.v (1887, 2005-11-22)
mi2c\verilog\rtl_encrypted\m3s002br.v.old (1926, 2001-10-02)
mi2c\verilog\rtl_encrypted\m3s003br.v (3664, 2005-11-22)
mi2c\verilog\rtl_encrypted\m3s003br.v.old (3710, 2001-10-02)
mi2c\verilog\rtl_encrypted\m3s004br.v (1013, 2005-11-22)
mi2c\verilog\rtl_encrypted\m3s004br.v.old (1054, 2001-10-02)
mi2c\verilog\rtl_encrypted\m3s005br.v (3592, 2005-11-22)
mi2c\verilog\rtl_encrypted\m3s005br.v.old (3638, 2001-10-02)
mi2c\verilog\rtl_encrypted\m3s006br.v (17787, 2005-11-22)
mi2c\verilog\rtl_encrypted\m3s006br.v.old (17830, 2001-10-02)
mi2c\verilog\rtl_encrypted\m3s007br.v (3702, 2005-11-22)
mi2c\verilog\rtl_encrypted\m3s007br.v.old (3742, 2001-10-02)
mi2c\verilog\rtl_encrypted\m3s008br.v (2148, 2005-11-22)
mi2c\verilog\rtl_encrypted\m3s008br.v.old (2190, 2001-10-02)
mi2c\verilog\rtl_encrypted\m3s009br.v (2295, 2005-11-22)
mi2c\verilog\rtl_encrypted\m3s009br.v.old (2334, 2001-10-02)
mi2c\verilog\rtl_encrypted\m3s010br.v (2213, 2005-11-22)
... ...
########################################################################
# ================== #
# COPYRIGHT NOTICE #
# ================== #
# Copyright Mentor Graphics Corporation 2001. All rights reserved. #
# This file and associated deliverables are the trade secrets, #
# confidential information and copyrighted works of Mentor Graphics #
# Corporation and are subject to the terms and conditions of Mentor #
# Graphics Corporation's Inventra IPX Product License Agreement. #
# #
# If you have further questions, please contact #
# Mentor Graphics' Support : #
# #
# Pre-sales Email: ipfpga_support@mentor.com #
# #
# Post-sales Email: support_net@mentor.com #
# Web: http://www.mentor.com/supportnet #
# #
########################################################################
###########################
mi2c IPX core
###########################
Core Version :- 5.3p1
This file describes the directory structure for this Inventra IPX core.
This version of the library is only suitable for evaluating the cores
targeted at Altera PLDs.
Other Vendor devices will be supported in the future.
docs\ Contains core data sheet and product
specification. Documents in Adobe PDF format.
vhdl\ VHDL fileset for core.
vhdl\template Contains a Quartus symbol file and a template
file for text based instantiation of core in HDL.
vhdl\rtl_sim ModelSim compiled test bench and core (from
source RTL). ModelSim script provided to run
simulation under ModelSim. Provided to
demonstrate core operation and to provide a
comparison for gate level simulation.
vhdl\gate_sim ModelSim compiled test bench.
ModelSim scripts provided to compile gate level
netlist, Altera library components and simulate
in test bench. Requires that LeonardoSpectrum
synthesis and Quartus place and route have been
completed.
vhdl\rtl_encrypted Encrypted RTL files for core, used during
LeonardoSpectrum synthesis.
vhdl\synth LeonardoSpectrum Synthesis scripts for core.
vhdl\synth\quartus Quartus Place and Route scripts.
Require LeonardoSpectrum synthesis to have
been performed.
verilog\ Verilog fileset for core.
verilog\template Contains a Quartus symbol file and a template
file for text based instantiation of core in HDL.
verilog\rtl_sim ModelSim compiled test bench and core (from
source RTL). ModelSim script provided to run
simulation under ModelSim. Provided to
demonstrate core operation and to provide a
comparison for gate level simulation.
verilog\gate_sim ModelSim compiled test bench.
ModelSim scripts provided to compile gate level
in netlist, Altera library components and
simulate test bench. Requires that
LeonardoSpectrum synthesis and Quartus place and
route have been completed.
verilog\rtl_encrypted Encrypted RTL files for core, used during
LeonardoSpectrum synthesis.
verilog\synth LeonardoSpectrum Synthesis scripts for core.
verilog\synth\quartus Quartus Place and Route scripts.
Require LeonardoSpectrum synthesis to have
been performed.
Please Note :
The scripts which perform the simulations, synthesis and place and
route all assume that the tools have been installed and the appropriate
additions made to the path and the system variables. This should happen
automatically as part of the software vendor's installation procedure.
The verification of the flow contained in these scripts was performed
using the software versions specified below. Also indicated for each
tool is the expected path and/or system variables that should have
been set up during the vendor tool installation. Should you experience
any problems running the scripts then please verify that the appropriate
path and/or system settings are set according to your installation.
Should you have different versions of the tools then the appropriate
settings should be used, however we cannot guarantee the flow using
older versions of the tools. The tool versions specified below should be
considered a minimum specification.
Simulation ModelSim SE 5.5c
path entry C:\Modeltech_5.5c\win32
Synthesis Leonardo Spectrum LS2001_1b_12
path entry C:\EXEMPLAR\LEOSPEC\LS2001_1b_12
Place & Route Quartus II 1.1 (no service packs installed)
path entry %QUARTUS_ROOTDIR%\bin
system variable QUARTUS_ROOTDIR = C:\quartus
近期下载者:
相关文件:
收藏者: