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所属分类VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:29KB
下载次数:4
上传日期:2010-12-13 09:59:38
上 传 者黄国猛
说明:  七人表决器当选举人大于或等于4时为通过,绿灯亮;反之不通过时,黄灯亮。描述时,只须检查每一个输入的状态(通过为“1”,不通过为“0”),并将这些状态值相加,判断状态值和即可选择输出。
(Seven voting machines when voters is greater than or equal to 4 through the green light the other hand does not pass, the yellow light. Description, just check the status of each input (through the " 1" , without " 0" ), and these states are added to determine the state values and to select the output.)

文件列表:[举报垃圾]
yy
..\LIB.DLS,113,2010-12-06
..\seg7d.acf,15667,2010-12-06
..\seg7d.fit,2846,2010-12-06
..\seg7d.hex,34004,2010-12-06
..\seg7d.hif,3312,2010-12-06
..\seg7d.mmf,340,2010-12-06
..\seg7d.ndb,1719,2010-12-06
..\seg7d.pin,5236,2010-12-06
..\seg7d.pof,55240,2010-12-06
..\seg7d.rpt,20547,2010-12-06
..\seg7d.scf,1895,2010-12-06
..\seg7d.snf,7398,2010-12-06
..\seg7d.sof,14437,2010-12-06
..\SEG7D.sym,316,2010-12-06
..\seg7d.ttf,59691,2010-12-06
..\seg7d.vhd,459,2010-12-06
..\U0409162.DLS,1154,2010-12-06
..\U5819412.DLS,4271,2010-12-06
..\U7355204.DLS,1494,2010-12-06

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