文件列表:

Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\ADDVB_Models_10.doc (229376, 2004-11-10)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\Dividers\Divider_RR_STG.v (5483, 2002-08-28)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\Dividers\Divider_STG_0.v (4463, 2004-11-10)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\Dividers\Divider_STG_0_sub.v (4392, 2004-11-10)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\Dividers\Divider_STG_1.v (6415, 2004-11-10)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\Dividers\t_Divider_RR_STG.v (2575, 2001-11-02)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\Dividers\_vti_cnf\Divider_RR_STG.v (258, 2002-08-28)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\Dividers\_vti_cnf\Divider_STG_0.v (258, 2000-06-28)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\Dividers\_vti_cnf\Divider_STG_0_sub.v (258, 2001-10-30)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\Dividers\_vti_cnf\Divider_STG_1.v (258, 2001-11-02)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\Dividers\_vti_cnf\t_Divider_RR_STG.v (258, 2001-11-02)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\Multipliers\Multiplier_ASM_0.v (3475, 2000-06-15)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\Multipliers\Multiplier_ASM_1.v (3410, 2000-06-15)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\Multipliers\Multiplier_Booth_STG_0.v (6366, 2004-10-12)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\Multipliers\Multiplier_Implicit_1.v (5857, 2002-08-28)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\Multipliers\Multiplier_Implicit_2.v (7370, 2000-05-31)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\Multipliers\Multiplier_RR_ASM.v (3294, 2002-08-28)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\Multipliers\Multiplier_STG_0.v (4341, 2004-10-12)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\Multipliers\Multiplier_STG_1.v (4524, 2000-06-15)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\Multipliers\Radix_4__STG_0.v (10340, 2004-05-11)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\Multipliers\_vti_cnf\Multiplier_ASM_0.v (258, 2000-06-15)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\Multipliers\_vti_cnf\Multiplier_ASM_1.v (258, 2000-06-15)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\Multipliers\_vti_cnf\Multiplier_Booth_STG_0.v (258, 2002-08-28)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\Multipliers\_vti_cnf\Multiplier_Implicit_1.v (258, 2002-08-28)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\Multipliers\_vti_cnf\Multiplier_Implicit_2.v (258, 2000-05-31)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\Multipliers\_vti_cnf\Multiplier_RR_ASM.v (258, 2002-08-28)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\Multipliers\_vti_cnf\Multiplier_STG_0.v (258, 2002-12-04)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\Multipliers\_vti_cnf\Multiplier_STG_1.v (258, 2000-06-15)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\Multipliers\_vti_cnf\Radix_4__STG_0.v (259, 2000-06-19)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 10\_vti_cnf\ADDVB_Models_10.doc (507, 2002-12-30)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 11\ADDVB_Models_11.doc (143360, 2002-12-30)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 11\BIST\ASIC_with_BIST.v (4144, 2002-02-22)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 11\BIST\t_ASIC_with_BIST.v (1310, 2002-02-22)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 11\BIST\_vti_cnf\ASIC_with_BIST.v (258, 2002-02-22)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 11\BIST\_vti_cnf\t_ASIC_with_BIST.v (258, 2002-02-22)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 11\JTAG\ASIC_with_TAP.v (2844, 2002-03-08)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 11\JTAG\Boundary_Scan_Register.v (1585, 2002-02-03)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 11\JTAG\BR_Cell.v (220, 2002-01-31)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 11\JTAG\BSC_Cell.v (432, 2002-01-24)
Advanced Digital Design with the Verilog HDL 源码 （ Michael D. Ciletti）\Advanced Digital Design with the Verilog HDL源码\Chapter 11\JTAG\Instruction_Decoder.v (1517, 2002-02-07)
... ...

5-10-2004 1. The Tap Controller has been revised. 8-11-2003 1. The models in this release reflect changes made for the revised version of the test released August 2003. 2. Testbenches for the models in Chapters 7-11 are included in the zip file. The remaining testbenches will also be added. If you need a particular model/testbench that is not included in this release please notify me and I will provide it. 3. Note: Some compilers are relaxed about requiring a redundant declaration of the size of an array whose size has already been declared by an output statement. Some of the models in this release have been changed to adhere to the tighter constraint. If you encounter a model that has not been changed please notify me. 4. In some cases, the file containing the model also contains its testbench. 5. Every effort has been made to ensure that these models are correct. Please notify me of any errors that you detect.

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