ISE_lab18
所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:4780KB
下载次数:17
上传日期:2010-12-19 16:26:51
上 传 者:
yuanou2007
说明: ChipScope软件调试数字系统设计
学会使用ChipScope在线逻辑分析仪工具对设计进行分析;
总结ChipScope软件调试与波形仿真的区别。
(ChipScope software debugging digital system design online learn to use ChipScope logic analyzer tool to analyze the design summary ChipScope software debugging and waveform simulation of the difference.)
文件列表:
ISE_lab18\Assembler\CONSTANT.TXT (2050, 2008-05-13)
ISE_lab18\Assembler\KCPSM3.EXE (89320, 2004-09-23)
ISE_lab18\Assembler\LABELS.TXT (95, 2008-05-13)
ISE_lab18\Assembler\PASS1.DAT (20389, 2008-05-13)
ISE_lab18\Assembler\PASS2.DAT (20389, 2008-05-13)
ISE_lab18\Assembler\PASS3.DAT (23755, 2008-05-13)
ISE_lab18\Assembler\PASS4.DAT (30902, 2008-05-13)
ISE_lab18\Assembler\PASS5.DAT (43985, 2008-05-13)
ISE_lab18\Assembler\PROGRAM.COE (7296, 2008-05-13)
ISE_lab18\Assembler\PROGRAM.DEC (5266, 2008-05-13)
ISE_lab18\Assembler\PROGRAM.FMT (11008, 2008-05-13)
ISE_lab18\Assembler\PROGRAM.HEX (7168, 2008-05-13)
ISE_lab18\Assembler\PROGRAM.LOG (13718, 2008-05-13)
ISE_lab18\Assembler\PROGRAM.M (3875, 2008-05-13)
ISE_lab18\Assembler\program.psm (10262, 2006-05-17)
ISE_lab18\Assembler\PROGRAM.V (23273, 2008-05-13)
ISE_lab18\Assembler\PROGRAM.VHD (19270, 2008-05-13)
ISE_lab18\Assembler\ROM_form.coe (66, 2008-05-13)
ISE_lab18\Assembler\ROM_form.v (15237, 2004-09-07)
ISE_lab18\Assembler\ROM_form.vhd (12737, 2003-07-28)
ISE_lab18\chipscope\bbfifo_16x8.vhd (6734, 2010-03-28)
ISE_lab18\chipscope\blk_mem_gen_ds512.pdf (1257529, 2008-05-15)
ISE_lab18\chipscope\blk_mem_gen_release_notes.txt (6020, 2008-05-15)
ISE_lab18\chipscope\chipscope.ise (308455, 2010-03-28)
ISE_lab18\chipscope\chipscope.ise_ISE_Backup (283317, 2007-01-29)
ISE_lab18\chipscope\chipscope.ntrc_log (1080, 2010-03-28)
ISE_lab18\chipscope\chipscope.restore (57144, 2010-03-28)
ISE_lab18\chipscope\chipscope_ise10migration.zip (2636314, 2008-05-15)
ISE_lab18\chipscope\chipscope_ise9migration.zip (1314335, 2007-01-29)
ISE_lab18\chipscope\chipscope_xdb\cst.xbcd (12238, 2010-03-28)
ISE_lab18\chipscope\chipscope_xdb\tmp\ise\version (138, 2010-03-28)
ISE_lab18\chipscope\chipscope_xdb\tmp\ise\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject (201, 2010-03-28)
ISE_lab18\chipscope\chipscope_xdb\tmp\ise\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject_StrTbl (25, 2010-03-28)
ISE_lab18\chipscope\chipscope_xdb\tmp\ise\__OBJSTORE__\HierarchicalDesign\__stored_object_table__ (60, 2010-03-28)
ISE_lab18\chipscope\chipscope_xdb\tmp\ise\__OBJSTORE__\PnAutoRun\Scripts\RunOnce_tcl (27, 2010-03-28)
ISE_lab18\chipscope\chipscope_xdb\tmp\ise\__OBJSTORE__\PnAutoRun\Scripts\RunOnce_tcl_StrTbl (3817, 2010-03-28)
ISE_lab18\chipscope\chipscope_xdb\tmp\ise\__OBJSTORE__\ProjectNavigator\dpm_project_main\dpm_project_main (90, 2010-03-28)
ISE_lab18\chipscope\chipscope_xdb\tmp\ise\__OBJSTORE__\ProjectNavigator\dpm_project_main\dpm_project_main_StrTbl (95, 2010-03-28)
ISE_lab18\chipscope\chipscope_xdb\tmp\ise\__OBJSTORE__\ProjectNavigator\dpm_project_main\NameMap (29, 2010-03-28)
ISE_lab18\chipscope\chipscope_xdb\tmp\ise\__OBJSTORE__\ProjectNavigator\dpm_project_main\NameMap_StrTbl (10, 2010-03-28)
... ...
The following files were generated for 'icon_pro' in directory
.\:
icon_pro.ncf:
Please see the core data sheet.
icon_pro.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
icon_pro.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
icon_pro.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
icon_pro.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
icon_pro_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
icon_pro_readme.txt:
Text file indicating the files generated and how they are used.
icon_pro_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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