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verilog_testbench_genetator

verilog testbench verilog perl perl verilog VERILOG TESTBEN gensim perl verilog

所属分类：VHDL/FPGA/Verilog
开发工具：Perl
文件大小：2KB
下载次数：74
上传日期：2010-12-22 11:00:42
上传者：ilovefdu

说明：这是一个perl程序只需要在cmd中运行，参数为你的Verilog名字功能是:半自动生成Verilog的testbench，提高编码效率
(#-----READ ME of verilog_tb_generate.pl----------------------| # | #-----copyright(C) Xzmeng 2010-------------------------------| # | #Date:2010-12-18 21:55:48------------------------------------| # | #Run the pl followed with the verlog file name,such as aaa.v | #Put the original verilog file(.v) in the current directory. | #------------------------------------------------------------| # | #And you need to gurrantee that there is only one "input" or | #"output" per line. | # | #------------------------------------------------------------| )

文件列表:

verilog_tb_generate.pl (5991, 2010-12-22)

#-----READ ME of verilog_tb_generate.pl----------------------| # | #-----copyright(C) Xzmeng 2010-------------------------------| # | #Date:2010-12-18 21:55:48------------------------------------| # | #Run the pl followed with the verlog file name,such as ***.v | #Put the original verilog file(.v) in the current directory. | #------------------------------------------------------------| # | #And you need to gurrantee that there is only one "input" or | #"output" per line. | # | #------------------------------------------------------------|

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