LIP2131CORE_dram_controller
所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:7946KB
下载次数:12
上传日期:2010-12-24 09:44:11
上 传 者:
joneychen12
说明: LIP2131 CORE Verilog DRAM Controller
文件列表:
bench\main.v (2638, 2007-02-24)
bench\sim_nc\architecture.v (115, 2007-02-24)
bench\sim_nc\run (154, 2007-02-24)
bench\sim_nc\sim.v (4, 2007-02-24)
bench\sim_nc\CVS\Entries (123, 2007-02-24)
bench\sim_nc\CVS\Repository (39, 2007-02-24)
bench\sim_nc\CVS\Root (38, 2007-02-24)
bench\sim_mc_Tek-5.2\run (250, 2007-02-24)
bench\sim_mc_Tek-5.2\sim.v (4440, 2007-02-24)
bench\sim_mc_Tek-5.2\output\pack\CVS\Entries (41, 2007-02-24)
bench\sim_mc_Tek-5.2\output\pack\CVS\Repository (59, 2007-02-24)
bench\sim_mc_Tek-5.2\output\pack\CVS\Root (38, 2007-02-24)
bench\sim_mc_Tek-5.2\output\normal\CVS\Entries (41, 2007-02-24)
bench\sim_mc_Tek-5.2\output\normal\CVS\Repository (61, 2007-02-24)
bench\sim_mc_Tek-5.2\output\normal\CVS\Root (38, 2007-02-24)
bench\sim_mc_Tek-5.2\output\downsample\CVS\Entries (41, 2007-02-24)
bench\sim_mc_Tek-5.2\output\downsample\CVS\Repository (65, 2007-02-24)
bench\sim_mc_Tek-5.2\output\downsample\CVS\Root (38, 2007-02-24)
bench\sim_mc_Tek-5.2\output\CVS\Entries (41, 2007-02-24)
bench\sim_mc_Tek-5.2\output\CVS\Repository (54, 2007-02-24)
bench\sim_mc_Tek-5.2\output\CVS\Root (38, 2007-02-24)
bench\sim_mc_Tek-5.2\debug_utils\diffall (414, 2007-02-24)
bench\sim_mc_Tek-5.2\debug_utils\generate_ppm (184, 2007-02-24)
bench\sim_mc_Tek-5.2\debug_utils\showRam.awk (1982, 2007-02-24)
bench\sim_mc_Tek-5.2\debug_utils\Tek-5.2_disp.stat (28, 2007-02-24)
bench\sim_mc_Tek-5.2\debug_utils\CVS\Entries (181, 2007-02-24)
bench\sim_mc_Tek-5.2\debug_utils\CVS\Repository (59, 2007-02-24)
bench\sim_mc_Tek-5.2\debug_utils\CVS\Root (38, 2007-02-24)
bench\sim_mc_Tek-5.2\CVS\Entries (105, 2007-02-24)
bench\sim_mc_Tek-5.2\CVS\Repository (47, 2007-02-24)
bench\sim_mc_Tek-5.2\CVS\Root (38, 2007-02-24)
bench\sim_mc_tcela-17\run (250, 2007-02-24)
bench\sim_mc_tcela-17\sim.v (4443, 2007-02-24)
bench\sim_mc_tcela-17\output\pack\CVS\Entries (41, 2007-02-24)
bench\sim_mc_tcela-17\output\pack\CVS\Repository (60, 2007-02-24)
bench\sim_mc_tcela-17\output\pack\CVS\Root (38, 2007-02-24)
... ...
IDCT TOOLS
--------------------------------------------------------------------------------
name : idct2yuv
aim : idct2yuv is a program which convert idct output coeffs in YUV
format
method : idct2yuv dump in RAM memory the idct coeffs from file
idct_output.dat
then, it dumps them (respecting picture size and format) in 3 files
file.Y file.U file.V
Command line : idct2yuv config_filename
input : idct_output_file (one pixel/line ie Quasar) [ use idct_split program if
needed (Mambo) ]
output : file.Y file.U file.V
structure : idct2yuv.cpp
exemple : config_idct2yuv can contain a line like: 800 600 4:2:0 input_filename
output_filename)
Then the prog will ask for idct output file.
idct output file looks like that:
01e
023
0f6
013
1ff
...
and so on with 9 bits pixels
--------------------------------------------------------------------------------
name : idct_split_4pix
aim : idct_split_4pix is a little program which split serialise lines
of 4 pixels. Use it to compare Mambo output from mpeg_ibus_interface
with output from Quasar.
method : it scans a file of 4 pixel rows and serialise them by creating new
file of 1 pixel/line.
Command line : idct_split_4pix < idct_output > idct_serial
structure : idct_split_4pix.c
exemple : see command line
--------------------------------------------------------------------------------
name : showRam
aim : showRam displays the content of Dram memory with or without
colors, packed or not packed.
method : load in RAM the entire DRAM memory and dumps it into 3 files file.y
file.u file.v in an order that enable 2D displaying.
input/output : type showRam --help for more details
structure : showRam.c showL.c showRam.h ( or use library lshow.a instead of
showL.c )
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