LIP1760CORE_dt_decoder
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：66KB
下载次数：5
上传日期：2010-12-24 10:12:24
上 传 者：
joneychen12
说明： DT Decoder include RISC16 & RISC32 Decoder Module
文件列表:
dt_dec_1\automake.log (2061, 2007-07-03)
dt_dec_1\dt_decode.cmd_log (67, 2007-07-03)
dt_dec_1\dt_decode.lso (6, 2007-07-03)
dt_dec_1\dt_decode.prj (28, 1980-01-01)
dt_dec_1\dt_decode.syr (5200, 2007-07-03)
dt_dec_1\dt_decode.v (15965, 2007-07-03)
dt_dec_1\dt_decode_summary.html (2633, 2007-07-03)
dt_dec_1\dt_decode_vhdl.prj (0, 2007-07-03)
dt_dec_1\dt_dec_1.dhp (366, 2007-07-03)
dt_dec_1\dt_dec_1.ise (4415, 2007-07-03)
dt_dec_1\dt_dec_1.ise_ISE_Backup (4415, 2007-07-03)
dt_dec_1\Project.dhp (969, 2007-07-03)
dt_dec_1\__projnav.log (86, 2007-07-03)
dt_dec_1\__projnav\dt_decode.xst (1103, 2007-07-03)
dt_dec_1\__projnav\dt_dec_1.gfl (251, 2007-07-03)
dt_dec_1\__projnav\dt_dec_1_flowplus.gfl (119, 2007-07-03)
dt_dec_1\__projnav\ednTOngd_tcl.rsp (54, 2007-07-03)
dt_dec_1\__projnav\parentCreateTimingConstraintsApp_tcl.rsp (11, 2007-07-03)
dt_dec_1\__projnav\runXst_tcl.rsp (37, 2007-07-03)
dt_dec_1\__projnav\sumrpt_tcl.rsp (18, 2007-07-03)
dt_dec_1\xst\work\hdllib.ref (63, 2007-07-03)
dt_dec_1\xst\work\vlg6F\dt__decode.bin (41735, 2007-07-03)
work\_info (264, 2007-07-03)
work\dt_decode\verilog.psm (98798, 2007-07-03)
work\dt_decode\_primary.dat (8077, 2007-07-03)
work\dt_decode\_primary.vhd (1428, 2007-07-03)
dt_decode.v (15965, 2007-07-03)
risc16_decode.v (15514, 2007-07-03)
risc16_decode.v.bak (16609, 2007-02-24)
risc32_decode.v (16329, 2007-02-24)
transcript (507, 2007-07-03)
dt_dec_1\xst\dump.xst\dt_decode.prj\ngx\opt (0, 2010-09-19)
dt_dec_1\xst\dump.xst\dt_decode.prj\ngx\notopt (0, 2010-09-19)
dt_dec_1\xst\dump.xst\dt_decode.prj\ngx (0, 2010-09-19)
dt_dec_1\xst\work\vlg6F (0, 2010-09-19)
dt_dec_1\xst\dump.xst\dt_decode.prj (0, 2010-09-19)
dt_dec_1\xst\work (0, 2010-09-19)
dt_dec_1\xst\dump.xst (0, 2010-09-19)
dt_dec_1\__projnav (0, 2010-09-19)
dt_dec_1\_xmsgs (0, 2010-09-19)
... ...
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