Altera_DDR_controller_core
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：735KB
下载次数：84
上传日期：2010-12-28 15:12:52
上 传 者：
markkknd
说明： Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等
(Altera DDR SDRAM Controller. Verilog source codes, description documents, DDR verilog model and simulation testbench are all included.)
文件列表:
doc\ddr_sdram.pdf (472801, 2000-05-30)
model\mt46v4m16.v (44955, 2000-03-29)
route\ddr_sdram.csf (10358, 2000-06-02)
route\ddr_sdram.esf (618, 2000-06-02)
route\ddr_sdram.psf (2443, 2000-06-02)
route\ddr_sdram.quartus (194, 2000-06-02)
route\ddr_sdram.vqm (595323, 2000-05-22)
route\pll1.v (4648, 2000-05-20)
simulation\ddr_compile_all.v (213, 2000-05-20)
simulation\ddr_sdram_tb.v (18362, 2010-12-20)
simulation\modelsim.ini (7728, 2000-05-21)
simulation\work\altclklock\verilog.psm (20672, 2000-05-21)
simulation\work\altclklock\_primary.dat (2333, 2000-05-21)
simulation\work\altclklock\_primary.vhd (899, 2000-05-21)
simulation\work\ddr_command\verilog.psm (46232, 2000-05-21)
simulation\work\ddr_command\_primary.dat (5126, 2000-05-21)
simulation\work\ddr_command\_primary.vhd (1327, 2000-05-21)
simulation\work\ddr_control_interface\verilog.psm (21720, 2000-05-21)
simulation\work\ddr_control_interface\_primary.dat (2785, 2000-05-21)
simulation\work\ddr_control_interface\_primary.vhd (1113, 2000-05-21)
simulation\work\ddr_data_path\verilog.psm (24088, 2000-05-21)
simulation\work\ddr_data_path\_primary.dat (3215, 2000-05-21)
simulation\work\ddr_data_path\_primary.vhd (817, 2000-05-21)
simulation\work\ddr_sdram\verilog.psm (28640, 2000-05-21)
simulation\work\ddr_sdram\_primary.dat (4552, 2000-05-21)
simulation\work\ddr_sdram\_primary.vhd (1085, 2000-05-21)
simulation\work\ddr_sdram_tb\verilog.psm (61744, 2000-05-21)
simulation\work\ddr_sdram_tb\_primary.dat (9399, 2000-05-21)
simulation\work\ddr_sdram_tb\_primary.vhd (102, 2000-05-21)
simulation\work\mt46v4m16\verilog.psm (232024, 2000-05-21)
simulation\work\mt46v4m16\_primary.dat (25110, 2000-05-21)
simulation\work\mt46v4m16\_primary.vhd (1174, 2000-05-21)
simulation\work\pll1\verilog.psm (4896, 2000-05-21)
simulation\work\pll1\_primary.dat (823, 2000-05-21)
simulation\work\pll1\_primary.vhd (256, 2000-05-21)
simulation\work\_info (1109, 2000-05-21)
source\altclklock.v (9281, 2000-05-20)
source\ddr_Command.v (16585, 2000-06-02)
source\ddr_control_interface.v (9424, 2000-06-02)
... ...
File/Directory Description
=============================================================================
\doc DDR SDRAM reference design documentation
\model Contains the verilog SDRAM model
\route Contains the Quartus 2000.05 project files a routed controller design
\simulation Contains the verilog testbench, modelsim project file, and library
\source Contains the verilog source files for the DDR SDRAM reference design
\synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
added by Shenzhi 2010.12.20
\simulation 下 ddr_sdram_tb.v文件中 不能使用 config关键词
解决方法：将所有“config”改成“Config”
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