XDS100v2_Schematic_(rev2)
所属分类：DSP编程
开发工具：C/C++
文件大小：1803KB
下载次数：120
上传日期：2011-01-03 09:04:20
上 传 者：
boboo
说明： ti 最新廉价仿真器 支持所有芯片 但只能在CCS4下使用
价格超低，性价比追XDS560了
(ti emulator supports all the latest low-cost chip, but can only be used in CCS4 low price, cost-effective to recover the XDS560)
文件列表:
XDS100v2 Schematic (rev2)\CPLD\xds100v2_cpld.ise (130950, 2010-04-26)
XDS100v2 Schematic (rev2)\CPLD\xds100v2_cpld.jed (17113, 2010-04-26)
XDS100v2 Schematic (rev2)\CPLD\xds100v2_cpld.ucf (705, 2010-04-07)
XDS100v2 Schematic (rev2)\CPLD\xds100v2_cpld.v (8200, 2010-04-26)
XDS100v2 Schematic (rev2)\design\fdti2232h.sch (38669, 2009-10-13)
XDS100v2 Schematic (rev2)\design\jtag.sch (40004, 2009-10-13)
XDS100v2 Schematic (rev2)\design\xds100v2-Component.pho (56174, 2009-10-13)
XDS100v2 Schematic (rev2)\design\xds100v2-Component.pos (5138, 2009-10-13)
XDS100v2 Schematic (rev2)\design\xds100v2-Copper.pho (27180, 2009-10-13)
XDS100v2 Schematic (rev2)\design\xds100v2-Drawings.pho (111632, 2009-10-13)
XDS100v2 Schematic (rev2)\design\xds100v2-drl.ps (32796, 2009-10-13)
XDS100v2 Schematic (rev2)\design\xds100v2-drl.rpt (700, 2009-10-13)
XDS100v2 Schematic (rev2)\design\xds100v2-Inner_L1.pho (143395, 2009-10-13)
XDS100v2 Schematic (rev2)\design\xds100v2-Inner_L2.pho (133939, 2009-10-13)
XDS100v2 Schematic (rev2)\design\xds100v2-Mask_Cmp.pho (15750, 2009-10-13)
XDS100v2 Schematic (rev2)\design\xds100v2-Mask_Cop.pho (10214, 2009-10-13)
XDS100v2 Schematic (rev2)\design\xds100v2-SilkS_Cmp.pho (83653, 2009-10-13)
XDS100v2 Schematic (rev2)\design\xds100v2-SilkS_Cop.pho (16743, 2009-10-13)
XDS100v2 Schematic (rev2)\design\xds100v2-SoldP_Cmp.pho (14112, 2009-10-13)
XDS100v2 Schematic (rev2)\design\xds100v2-SoldP_Cop.pho (9288, 2009-10-13)
XDS100v2 Schematic (rev2)\design\xds100v2.brd (383919, 2009-10-13)
XDS100v2 Schematic (rev2)\design\xds100v2.cache.dcm (230, 2009-10-13)
XDS100v2 Schematic (rev2)\design\xds100v2.cache.lib (12135, 2009-10-13)
XDS100v2 Schematic (rev2)\design\xds100v2.cmp (9955, 2009-10-13)
XDS100v2 Schematic (rev2)\design\xds100v2.drl (2826, 2009-10-13)
XDS100v2 Schematic (rev2)\design\xds100v2.lst (6962, 2009-10-13)
XDS100v2 Schematic (rev2)\design\xds100v2.net (19034, 2009-10-13)
XDS100v2 Schematic (rev2)\design\xds100v2.pro (1152, 2009-10-13)
XDS100v2 Schematic (rev2)\design\xds100v2.sch (4293, 2009-10-13)
XDS100v2 Schematic (rev2)\design\xds100v2_BOM.xls (33280, 2009-10-13)
XDS100v2 Schematic (rev2)\design\xds100v2_pcblib.brd (41032, 2009-10-13)
XDS100v2 Schematic (rev2)\lib\xds100v2_pcblib.mdc (290, 2009-10-13)
XDS100v2 Schematic (rev2)\lib\xds100v2_pcblib.mod (40359, 2009-10-13)
XDS100v2 Schematic (rev2)\lib\xds100_v2.dcm (286, 2009-10-13)
XDS100v2 Schematic (rev2)\lib\xds100_v2.lib (15632, 2009-10-13)
XDS100v2 Schematic (rev2)\license\epk_license_agreement.pdf (49176, 2009-10-16)
XDS100v2 Schematic (rev2)\MProg\XDS100v2.ept (1660, 2009-10-13)
XDS100v2 Schematic (rev2)\Schematic\xds100v2schematic.pdf (242516, 2009-10-13)
... ...
XDS100v2 EPK
Updated April 28, 2010
PURPOSE
To provide XDS100v2 reference design and additional information to enable 3rd parties to build the XDS100v2 hardware.
CONTENTS
/CPLD folder
contains CPLD JED and source files
/design and /lib folders
KICAD SOURCES
./xds100v2.pro KICAD PROJECT FILE
./xds100v2.sch TOP SCHEMATIC FILE
./ftdi2232h.sch FTDI USB CHIP SCHEMATIC SHEET
./jtag.sch JTAG CONNECTOR SCHEMATIC SHEET
../lib/xds100v2.lib SCHEMATIC LIBRARY
../lib/xds100v2_pcblib.mod MODULE (Footprint) LIBRARY
./xds100v2_pcblib.brd SOURCE FILE FOR PCB MODULE FOOTPRINTS
./xds100v2.brd PCB FILE
KICAD OUTPUTS
xds100v2.net NETLIST
GERBER FILES
xds100v2-Silks_Cmp.pho Top Silkscreen
xds100v2-Mask_Cmp.pho Top SolderMask
xds100v2-Component.pho Top Copper
xds100v2-Inner_L1.pho Inner Layer 1 Copper (Positive)
xds100v2-Inner_L2.pho Inner Layer 2 Copper (Positive)
xds100v2-Copper.pho Bottom Copper
xds100v2-Mask_Cop.pho Bottom SolderMask
xds100v2-Silks_Cop.pho Bottom Silkscreen
xds100v2-Drawings.pho Board Outline, Mechanical Dimensions
xds100v2-SoldP_Cmp.pho Top Solder Paste
xds100v2-SoldP_Cop.pho Bottom Solder Paste
ASSEMBLY FILES
XDS100v2_BOM.xls Bill of Materials (Excel 2003)
xds100v2-Component.pos X,Y,Rot Position File for Component Placement
/MProg folder
contains MProg script file
/Schematic folder
contains XDS100v2 schematic in .pdf format
KNOWN BUG FOR EVM DESIGNERS
The CPLD programming pins were moved to Port BCBUS 4,5,6,7 to make room for the B port to be used as UART.
However, in the UART mode these pins are mostly used as status. it appears there isn't a way to turn this behavior off, so if we continue using these pins as a recommendation - then we'll have CPLD TCK, TDI toggling based on UART activity. TMS is connected to an input pin so it could conceiveably change state, and something might get scanned into the CPLD that affects it's functionality
RECOMMENDED FIX
BCBUS 1, 2, 5, and 6 are the only free pins on BCBUS when
the FTDI chip B port is in UART mode.
We should change the recommendation for CPLD in circuit programming to use:
BCBUS1 -> CPLD TCK
BCBUS2 -> CPLD TDI
BCBUS5 -> CPLD TDO
BCBUS6 -> CPLD TMS
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