Oscilloscope_V1.0
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：50KB
下载次数：6
上传日期：2011-01-07 23:05:46
上 传 者：
joneychen12
说明： XAPP Oscillscope VHDL code
文件列表:
Source\PocketC\Oscilloscope.pc (2543, 2001-05-07)
Source\PocketC\small1.bmp (1222, 2001-03-19)
Source\PocketC\Thumbs.db (4096, 2011-01-06)
Source\PocketC\Xilinx.bmp (190, 2000-07-06)
Source\VHDL\multi_oscope.vhd (37113, 2001-06-13)
Source\VHDL\shift16.vhd (1757, 2001-06-12)
Source\VHDL\shift8.vhd (1849, 2001-06-12)
Source\VHDL\top_level.ucf (5325, 2001-05-07)
Source\VHDL\top_level.vhd (8421, 2001-06-12)
Source\VHDL\top_level_tb.vhd (4731, 2001-05-07)
Source\VHDL\upcnt5.vhd (1535, 2001-06-12)
Oscilloscope.prc (41299, 2001-05-07)
top_level.jed (155226, 2001-06-13)
Source\PocketC (0, 2011-01-06)
Source\VHDL (0, 2001-06-13)
Source (0, 2001-06-13)
Oscilloscope_ver1.0.zip
This zip file contains the following source code.
VHDL SOURCE CODE:
-----------------
top_level.vhd -- Top level VHDL file
+ multi_oscope.vhd -- State machine implementation
+ shift16.vhd -- 16 bit shift register
+ shift8.vhd -- 8 bit shift register
+ upcnt5.vhd -- 5 bit up counter
top_level.ucf -- Xilinx "User Constraints File". Used by Xilinx WebPACK software
to assign pins
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