文件列表:

delivery (0, 2008-10-13)
delivery\design (0, 2008-10-13)
delivery\design\verilog_src (0, 2008-10-13)
delivery\design\verilog_src\ds1wm (0, 2008-10-13)
delivery\design\verilog_src\ds1wm\clk_prescaler.v (5498, 2008-10-13)
delivery\design\verilog_src\ds1wm\ds1wm.v (3836, 2008-10-13)
delivery\design\verilog_src\ds1wm\onewiremaster.v (49417, 2008-10-13)
delivery\design\verilog_src\ds1wm\one_wire_interface.v (13570, 2008-10-13)
delivery\design\verilog_src\ds1wm\one_wire_io.v (2379, 2008-10-13)
delivery\design\vhdl_src (0, 2008-10-13)
delivery\design\vhdl_src\ds1wm (0, 2008-10-13)
delivery\design\vhdl_src\ds1wm\clk_prescaler.vhd (8052, 2008-10-13)
delivery\design\vhdl_src\ds1wm\ds1wm.vhd (14169, 2008-10-13)
delivery\design\vhdl_src\ds1wm\onewiremaster.vhd (58520, 2008-10-13)
delivery\design\vhdl_src\ds1wm\one_wire_interface.vhd (15236, 2008-10-13)
delivery\design\vhdl_src\ds1wm\one_wire_io.vhd (2695, 2008-10-13)
delivery\doc (0, 2008-10-13)
delivery\doc\DS1WM_Datasheet.pdf (121187, 2008-10-13)
delivery\doc\release_notes.pdf (85099, 2008-10-13)
delivery\verification (0, 2008-10-13)
delivery\verification\verilog_src (0, 2008-10-13)
delivery\verification\verilog_src\testbench (0, 2008-10-13)
delivery\verification\verilog_src\testbench\clkgen (0, 2008-10-13)
delivery\verification\verilog_src\testbench\clkgen\clkgen.v (3271, 2008-10-13)
delivery\verification\verilog_src\testbench\cpu_bfm (0, 2008-10-13)
delivery\verification\verilog_src\testbench\cpu_bfm\cpu_bfm.v (20936, 2008-10-13)
delivery\verification\verilog_src\testbench\ow_slave (0, 2008-10-13)
delivery\verification\verilog_src\testbench\ow_slave\cmd_ctrl.v (7829, 2008-10-13)
delivery\verification\verilog_src\testbench\ow_slave\iox.v (12040, 2008-10-13)
delivery\verification\verilog_src\testbench\ow_slave\ow_slave.v (1709, 2008-10-13)
delivery\verification\verilog_src\testbench\scoreboard (0, 2008-10-13)
delivery\verification\verilog_src\testbench\scoreboard\scoreboard.v (6360, 2008-10-13)
delivery\verification\verilog_src\testbench\tb_ds1wm (0, 2008-10-13)
delivery\verification\verilog_src\testbench\tb_ds1wm\tb_ds1wm.v (844, 2008-10-13)
delivery\verification\verilog_src\testbench\tb_ds1wm\tc_ds1wm.v (2303, 2008-10-13)
delivery\verification\verilog_src\tests (0, 2008-10-13)
delivery\verification\verilog_src\tests\cmd_recognition (0, 2008-10-13)
delivery\verification\verilog_src\tests\cmd_recognition\nc_rundir (0, 2008-10-13)
delivery\verification\verilog_src\tests\cmd_recognition\nc_rundir\cds.lib (94, 2008-10-13)
... ...

This delivery package contains synthesizable VHDL RTL for the DS1WM block. The RTL is located under design/vhdl_src/ds1wm. This delivery package contains synthesizable Verilog RTL for the DS1WM block. The RTL is located under design/verilog_src/ds1wm. The testbench is implemented in verilog. This is located under; verification/verilog_src/testbench There are testcases that demonstrates a single search rom, multiple one wire network with search rom, scratch pad integrity and an exhaustive command recognition testcases. These testcases are located: verification/verilog_src/tests/single_search_rom verification/verilog_src/tests/multi_ow_network verification/verilog_src/tests/scratchpad_integrity verification/verilog_src/tests/cmd_recognition Each testcase comes with a run script for users that have ncsim installed. For usage instructions, please see the README file in the test directory. Release notes and a datasheet can be found in the "doc" directory.

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