CPU(4)
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：591KB
下载次数：31
上传日期：2015-01-06 09:55:18
上 传 者：
pwq296306654
说明： 基于ISE XILINX14.7开发的单周期CPU的基础指令实现代码 VERILOG
(VERILOG implementation code base based on single-cycle instruction CPU ISE XILINX14.7 development of)
文件列表:
CPU(4)\.lso (6, 2014-11-25)
CPU(4)\Addr.v (133, 2014-11-25)
CPU(4)\AddrImm.v (106, 2014-11-25)
CPU(4)\Addr_Jump.v (133, 2014-11-25)
CPU(4)\ANDcomponent.v (147, 2014-11-25)
CPU(4)\Control.v (2279, 2014-11-27)
CPU(4)\CPU.cmd_log (92, 2014-11-25)
CPU(4)\CPU.gise (9979, 2014-11-27)
CPU(4)\CPU.lso (6, 2014-11-25)
CPU(4)\CPU.prj (482, 2014-11-25)
CPU(4)\CPU.stx (3033, 2014-11-25)
CPU(4)\CPU.syr (6069, 2014-11-25)
CPU(4)\CPU.v (3412, 2014-11-27)
CPU(4)\CPU.xise (38239, 2014-11-27)
CPU(4)\CPU.xst (133, 2014-11-25)
CPU(4)\CPU_beh.prj (568, 2014-11-25)
CPU(4)\CPU_envsettings.html (10191, 2014-11-27)
CPU(4)\CPU_isim_beh.exe (94720, 2014-11-25)
CPU(4)\CPU_summary.html (4424, 2014-11-27)
CPU(4)\CPU_TF.v (1229, 2014-11-27)
CPU(4)\CPU_TF_beh.prj (486, 2014-11-27)
CPU(4)\CPU_TF_isim_beh.exe (94720, 2014-11-27)
CPU(4)\CPU_TF_isim_beh.wdb (54820, 2014-11-27)
CPU(4)\CPU_TF_stx_beh.prj (693, 2014-11-25)
CPU(4)\CPU_xst.xrpt (9399, 2014-11-25)
CPU(4)\Data_memory.v (802, 2014-11-27)
CPU(4)\dsadsa.v (1698, 2014-11-25)
CPU(4)\Extend.v (302, 2014-11-25)
CPU(4)\fuse.log (2565, 2014-11-27)
CPU(4)\fuse.xmsgs (695, 2014-11-27)
CPU(4)\fuseRelaunch.cmd (196, 2014-11-27)
CPU(4)\GetCode.prj (26, 2014-11-25)
CPU(4)\GetCode.stx (1437, 2014-11-25)
CPU(4)\GetCode.v (2684, 2014-11-27)
CPU(4)\GetCode.xst (137, 2014-11-25)
CPU(4)\GetCode_isim_beh.exe (94720, 2014-11-27)
CPU(4)\GetCode_isim_beh1.wdb (4923, 2014-11-25)
CPU(4)\Init.v (529, 2014-11-25)
CPU(4)\iseconfig\CPU.projectmgr (7388, 2014-11-27)
CPU(4)\iseconfig\CPU.xreport (20314, 2014-11-27)
... ...
近期下载者：
相关文件：
收藏者：