GaussSmooth
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：1960KB
下载次数：16
上传日期：2015-01-13 15:56:32
上 传 者：
样子1
说明： 图像处理，高斯平滑（VHDL）实现了去除高斯噪声的功能，希望对大家有帮助
(Image processing, Gaussian smoothing (VHDL))
文件列表:
netlist\adder_subtracter_spartan3e_7_0_0791f37e47b55236.edn (25424, 2009-03-26)
netlist\adder_subtracter_spartan3e_7_0_0791f37e47b55236.ngo (8870, 2009-03-26)
netlist\adder_subtracter_spartan3e_7_0_1c4ac2e2d5ff1107.edn (22331, 2009-03-26)
netlist\adder_subtracter_spartan3e_7_0_1c4ac2e2d5ff1107.ngo (7501, 2009-03-26)
netlist\adder_subtracter_spartan3e_7_0_9ea91c5999e9d4e6.edn (23880, 2009-03-26)
netlist\adder_subtracter_spartan3e_7_0_9ea91c5999e9d4e6.ngo (8201, 2009-03-26)
netlist\binary_counter_spartan3e_9_1_d08bd33ad9db9366.edn (8352, 2008-12-17)
netlist\binary_counter_spartan3e_9_1_d08bd33ad9db9366.ngo (2590, 2009-03-26)
netlist\binary_counter_spartan3e_9_1_d08bd33ad9db9366_c_counter_binary_v9_1_xst_1.ngc (10542, 2008-12-17)
netlist\bmg_24_s3e_113c31da7ab05ccb.mif (10240, 2008-12-17)
netlist\bmg_24_s3e_113c31da7ab05ccb.ngc (19475, 2008-12-17)
netlist\device_usage_statistics.html (58154, 2009-03-26)
netlist\gausssmooth.vhd (149819, 2009-03-26)
netlist\gausssmooth_cw.bgn (8497, 2009-03-26)
netlist\gausssmooth_cw.bit (283874, 2009-03-26)
netlist\gausssmooth_cw.bld (4102, 2009-03-26)
netlist\gausssmooth_cw.cmd_log (1549, 2009-03-26)
netlist\gausssmooth_cw.drc (3996, 2009-03-26)
netlist\gausssmooth_cw.gise (1065, 2015-01-13)
netlist\gausssmooth_cw.lso (6, 2009-03-26)
netlist\gausssmooth_cw.ncd (67173, 2009-03-26)
netlist\gausssmooth_cw.ngc (67031, 2009-03-26)
netlist\gausssmooth_cw.ngd (193760, 2009-03-26)
netlist\gausssmooth_cw.ngr (135735, 2009-03-26)
netlist\gausssmooth_cw.ntrc_log (132, 2009-03-26)
netlist\gausssmooth_cw.pad (13561, 2009-03-26)
netlist\gausssmooth_cw.par (4290, 2009-03-26)
netlist\gausssmooth_cw.pcf (34669, 2009-03-26)
netlist\gausssmooth_cw.prj (61, 2009-03-26)
netlist\gausssmooth_cw.ptwx (16849, 2009-03-26)
netlist\gausssmooth_cw.restore (58889, 2009-03-26)
netlist\gausssmooth_cw.sdc (47, 2009-03-26)
netlist\gausssmooth_cw.sgp (0, 2009-03-26)
netlist\gausssmooth_cw.stx (0, 2009-03-26)
netlist\gausssmooth_cw.syr (94769, 2009-03-26)
netlist\gausssmooth_cw.twr (15727, 2009-03-26)
netlist\gausssmooth_cw.twx (33361, 2009-03-26)
netlist\gausssmooth_cw.ucf (135, 2009-03-26)
netlist\gausssmooth_cw.unroutes (156, 2009-03-26)
netlist\gausssmooth_cw.ut (392, 2009-03-26)
... ...
The following files were generated for 'adder_subtracter_spartan3e_7_0_0791f37e47b55236' in directory
.\:
adder_subtracter_spartan3e_7_0_0791f37e47b55236.edn:
Electronic Data Netlist (EDN) file containing the information
required to implement the module in a Xilinx (R) FPGA.
adder_subtracter_spartan3e_7_0_0791f37e47b55236.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
adder_subtracter_spartan3e_7_0_0791f37e47b55236.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
adder_subtracter_spartan3e_7_0_0791f37e47b55236.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
adder_subtracter_spartan3e_7_0_0791f37e47b55236.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
adder_subtracter_spartan3e_7_0_0791f37e47b55236.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
adder_subtracter_spartan3e_7_0_0791f37e47b55236_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
adder_subtracter_spartan3e_7_0_0791f37e47b55236_readme.txt:
Text file indicating the files generated and how they are used.
adder_subtracter_spartan3e_7_0_0791f37e47b55236_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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