eetop.cn_Booth_mutipler_v2
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：676KB
下载次数：27
上传日期：2015-01-18 21:24:59
上 传 者：
哇哈哈哈
说明： 新型32位booth乘法器的实现,使用verilog的一种新型乘法器改进实现
(The new 32 booth multiplier implementations)
文件列表:
Booth_mutipler\src\tbooth_com.v (4010, 2006-09-16)
Booth_mutipler\src\booth_com.v (4039, 2006-08-28)
Booth_mutipler\src\tbooth_pipeline.v (4740, 2006-09-16)
Booth_mutipler\src\booth_pipeline.v (7578, 2006-09-16)
Booth_mutipler\src (0, 2006-08-23)
Booth_mutipler\sim\work\_info (941, 2006-09-16)
Booth_mutipler\sim\work\booth_pipeline\_primary.vhd (376, 2006-09-16)
Booth_mutipler\sim\work\booth_pipeline\verilog.asm (21846, 2006-09-16)
Booth_mutipler\sim\work\booth_pipeline\_primary.dat (3757, 2006-09-16)
Booth_mutipler\sim\work\booth_pipeline (0, 2006-08-27)
Booth_mutipler\sim\work\tbooth_pipeline\_primary.vhd (90, 2006-09-16)
Booth_mutipler\sim\work\tbooth_pipeline\verilog.asm (17203, 2006-09-16)
Booth_mutipler\sim\work\tbooth_pipeline\_primary.dat (2324, 2006-09-16)
Booth_mutipler\sim\work\tbooth_pipeline (0, 2006-08-27)
Booth_mutipler\sim\work\tbooth_com\_primary.vhd (139, 2006-09-16)
Booth_mutipler\sim\work\tbooth_com\verilog.asm (32970, 2006-09-16)
Booth_mutipler\sim\work\tbooth_com\_primary.dat (2170, 2006-09-16)
Booth_mutipler\sim\work\tbooth_com (0, 2006-08-28)
Booth_mutipler\sim\work\booth_com\_primary.vhd (389, 2006-09-16)
Booth_mutipler\sim\work\booth_com\verilog.asm (28251, 2006-09-16)
Booth_mutipler\sim\work\booth_com\_primary.dat (1800, 2006-09-16)
Booth_mutipler\sim\work\booth_com (0, 2006-08-28)
Booth_mutipler\sim\work (0, 2006-08-23)
Booth_mutipler\sim\vsim.wlf (106496, 2006-09-16)
Booth_mutipler\sim\booth_mul.cr.mti (2, 2006-09-15)
Booth_mutipler\sim\vlog.opt (6, 2006-08-27)
Booth_mutipler\sim\maxii\_info (3346, 2006-09-05)
Booth_mutipler\sim\maxii\@m@a@x@i@i_@p@r@i@m_@d@f@f@e\_primary.vhd (179, 2006-09-05)
Booth_mutipler\sim\maxii\@m@a@x@i@i_@p@r@i@m_@d@f@f@e\verilog.asm (1480, 2006-09-05)
Booth_mutipler\sim\maxii\@m@a@x@i@i_@p@r@i@m_@d@f@f@e\_primary.dat (1292, 2006-09-05)
Booth_mutipler\sim\maxii\@m@a@x@i@i_@p@r@i@m_@d@f@f@e (0, 2006-09-05)
Booth_mutipler\sim\maxii\maxii_dffe\_primary.vhd (354, 2006-09-05)
Booth_mutipler\sim\maxii\maxii_dffe\verilog.asm (10011, 2006-09-05)
Booth_mutipler\sim\maxii\maxii_dffe\_primary.dat (921, 2006-09-05)
Booth_mutipler\sim\maxii\maxii_dffe (0, 2006-09-05)
Booth_mutipler\sim\maxii\maxii_latch\_primary.vhd (313, 2006-09-05)
Booth_mutipler\sim\maxii\maxii_latch\verilog.asm (8310, 2006-09-05)
Booth_mutipler\sim\maxii\maxii_latch\_primary.dat (860, 2006-09-05)
Booth_mutipler\sim\maxii\maxii_latch (0, 2006-09-05)
Booth_mutipler\sim\maxii\maxii_mux21\_primary.vhd (270, 2006-09-05)
... ...
计算机组成原理中的Booth乘法器，相信大家都是非常熟悉的了。我在这里用了两种方法实现。
1.booth_com.v。首先把输入的两个操作数锁存一拍，然后用组合逻辑算出乘积，通过寄存器输出。
tbooth_com.v。booth_com的testbench。利用随机函数$random产生两个机数，然后将booth_com算出的结果与预期结果进行比较，
并将比较的结果写入report_com文件。
2.booth_pipeline.v。用四级流水线实现的4位Booth算法乘法器。相信对大家理解流水线会有所帮助。
tbooth_pipeline.v。booth_pipeline的testbench。利用随机函数$random产生两个机数，然后将booth_pipeline算出的结果与预期
结果进行比较,并将比较的结果写入report_pipeline文件。
两个源文件均在quartus5.0中实现并通过时序仿真验证。
欢迎大家多提宝贵意见：liyun022@163.com
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