VGA
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：54KB
下载次数：1
上传日期：2015-01-20 21:27:07
上 传 者：
3613470
说明： quartus ii verilog hdl 实现VGA时序及显示的工程和源程序
(quartus ii verilog hdl vga timing project
and source code)
文件列表:
VGA\db\logic_util_heursitic.dat (6336, 2013-07-16)
VGA\db\prev_cmp_VGA.qmsg (4312, 2013-07-16)
VGA\db\VGA.db_info (138, 2014-07-31)
VGA\db\VGA.sld_design_entry.sci (197, 2014-07-31)
VGA\incremental_db\compiled_partitions\VGA.db_info (138, 2014-07-31)
VGA\VGA.asm.rpt (7378, 2013-07-16)
VGA\VGA.done (26, 2013-07-16)
VGA\VGA.fit.rpt (115127, 2013-07-16)
VGA\VGA.fit.smsg (567, 2013-07-16)
VGA\VGA.fit.summary (594, 2013-07-16)
VGA\VGA.flow.rpt (7788, 2013-07-16)
VGA\VGA.jdi (311, 2013-07-16)
VGA\VGA.map.rpt (22748, 2013-07-16)
VGA\VGA.map.summary (457, 2013-07-16)
VGA\VGA.pin (20256, 2013-07-16)
VGA\VGA.pof (524492, 2013-07-16)
VGA\VGA.qpf (1266, 2013-07-16)
VGA\VGA.qsf (3707, 2014-07-31)
VGA\VGA.qws (1259, 2013-07-17)
VGA\VGA.sof (358324, 2013-07-16)
VGA\VGA.sta.rpt (177028, 2013-07-16)
VGA\VGA.sta.summary (1726, 2013-07-16)
VGA\VGA.v (3873, 2009-08-14)
VGA\incremental_db\compiled_partitions (0, 2014-07-31)
VGA\db (0, 2014-07-31)
VGA\incremental_db (0, 2014-07-04)
VGA (0, 2014-07-04)
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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