rtl_wangjiangxing
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：15KB
下载次数：68
上传日期：2015-01-29 18:43:47
上 传 者：
鹏001
说明： ecc椭圆算法RTL,verilog源代码经过验证，用于FPGA或者ASIC
(ECC elliptic curve encryption algorithm for Verilog implementation)
文件列表:
rtl_wangjiangxing\adder.v (3178, 2012-04-17)
rtl_wangjiangxing\ECC_controller.v (8688, 2012-04-17)
rtl_wangjiangxing\ECC_processor.v (16113, 2012-04-17)
rtl_wangjiangxing\fifo_io.v (4971, 2012-04-17)
rtl_wangjiangxing\fifo_readonly.v (3306, 2012-04-17)
rtl_wangjiangxing\point_add.v (11863, 2012-04-17)
rtl_wangjiangxing\prime_inv256.v (7340, 2012-04-17)
rtl_wangjiangxing\prime_mul256.v (4116, 2012-04-17)
rtl_wangjiangxing\prime_PointK.v (5825, 2012-04-17)
rtl_wangjiangxing\test.v (14810, 2012-04-17)
rtl_wangjiangxing (0, 2014-09-26)
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