tdc-core

所属分类:VHDL/FPGA/Verilog
开发工具:Verilog
文件大小:984KB
下载次数:5
上传日期:2015-02-01 08:11:16
上 传 者sh-1993
说明:  用于Spartan-6 FPGA的26ps RMS时间-数字转换器(TDC)核心
(A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs)

文件列表:
core (0, 2011-12-03)
core\Manifest.py (241, 2011-12-03)
core\tdc.vhd (8508, 2011-12-03)
core\tdc_channel.vhd (7085, 2011-12-03)
core\tdc_channelbank.vhd (8187, 2011-12-03)
core\tdc_channelbank_multi.vhd (12535, 2011-12-03)
core\tdc_channelbank_single.vhd (7178, 2011-12-03)
core\tdc_controller.vhd (12543, 2011-12-03)
core\tdc_delayline.vhd (4584, 2011-12-03)
core\tdc_divider.vhd (3894, 2011-12-03)
core\tdc_freqc.vhd (5664, 2011-12-03)
core\tdc_lbc.vhd (5945, 2011-12-03)
core\tdc_ordertaps.vhd (25077, 2011-12-03)
core\tdc_package.vhd (14586, 2011-12-03)
core\tdc_psync.vhd (2956, 2011-12-03)
core\tdc_ringosc.vhd (2937, 2011-12-03)
demo (0, 2011-12-03)
demo\boards (0, 2011-12-03)
demo\boards\spec (0, 2011-12-03)
demo\boards\spec\rotest (0, 2011-12-03)
demo\boards\spec\rotest\Makefile (850, 2011-12-03)
demo\boards\spec\rotest\build (0, 2011-12-03)
demo\boards\spec\rotest\build\.keep_me (0, 2011-12-03)
demo\boards\spec\rotest\rotest.ucf (340, 2011-12-03)
demo\boards\spec\rotest\rotest.vhd (2425, 2011-12-03)
demo\boards\spec\rotest\rotest.xst (111, 2011-12-03)
demo\boards\spec\rtl (0, 2011-12-03)
demo\boards\spec\rtl\lm32_include.v (11965, 2011-12-03)
demo\boards\spec\rtl\setup.v (935, 2011-12-03)
demo\boards\spec\rtl\system.v (11258, 2011-12-03)
demo\boards\spec\sources.mak (1128, 2011-12-03)
demo\boards\spec\synthesis (0, 2011-12-03)
demo\boards\spec\synthesis\Makefile.xst (833, 2011-12-03)
demo\boards\spec\synthesis\build (0, 2011-12-03)
demo\boards\spec\synthesis\build\.keep_me (0, 2011-12-03)
demo\boards\spec\synthesis\common.mak (527, 2011-12-03)
demo\boards\spec\synthesis\common.ucf (2348, 2011-12-03)
demo\boards\spec\synthesis\floorplan_oscillators.py (585, 2011-12-03)
... ...

Time to Digital Converter core for Spartan-6 FPGAs ================================================== Directory organization: core/ VHDL sources of the TDC core. demo/ Demonstration design for the SPEC board. doc/ Documentation. hostif/ Optional host interface. tb/ Test benches.

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