an483

所属分类:VHDL/FPGA/Verilog
开发工具:PDF
文件大小:1433KB
下载次数:41
上传日期:2011-02-01 01:57:33
上 传 者hw342
说明:  The Altera® Triple Speed Ethernet (TSE) data path reference design provides a sample SOPC Builder system using the Altera TSE MegaCore® function with two serial transceivers. This reference design demonstrates the operation of the Altera TSE MegaCore function up to the maximum wire-speed performance in hardware. The design enables you to evaluate the TSE MegaCore function for integration into Altera FPGA designs.

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an483.pdf (1694236, 2011-02-01)

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