文件列表:

2013.3 (0, 2013-12-11)
2013.3\AC701 (0, 2013-12-11)
2013.3\AC701\run_here (0, 2013-12-21)
2013.3\AC701\run_here\build_bitstream.tcl (2316, 2013-10-14)
2013.3\AC701\scan_time (0, 2013-12-11)
2013.3\AC701\scan_time\es_pc_host.tcl (29573, 2013-10-29)
2013.3\AC701\scan_time\load_vivado_scans.tcl (494, 2013-10-02)
2013.3\AC701\scan_time\run_eyescan.tcl (3434, 2013-10-29)
2013.3\AC701\source (0, 2013-12-11)
2013.3\AC701\source\constraints (0, 2013-12-11)
2013.3\AC701\source\constraints\xilinx_pcie_7x_ep_x4g2_AC701.xdc (7559, 2013-09-29)
2013.3\AC701\source\core (0, 2013-12-11)
2013.3\AC701\source\core\pcie_7x_0.xci (63347, 2013-09-22)
2013.3\AC701\source\custom_ip (0, 2013-12-17)
2013.3\AC701\source\custom_ip\drp_bridge_ip (0, 2013-12-11)
2013.3\AC701\source\custom_ip\drp_bridge_ip\package (0, 2013-12-11)
2013.3\AC701\source\custom_ip\drp_bridge_ip\package\component.xml (37189, 2013-12-16)
2013.3\AC701\source\custom_ip\drp_bridge_ip\package\drp_bridge_0 (0, 2013-12-11)
2013.3\AC701\source\custom_ip\drp_bridge_ip\package\drp_bridge_0\drp_bridge_0.xci (3473, 2013-06-27)
2013.3\AC701\source\custom_ip\drp_bridge_ip\package\drp_bridge_0\drp_bridge_0.xml (31610, 2013-06-27)
2013.3\AC701\source\custom_ip\drp_bridge_ip\package\xgui (0, 2013-12-11)
2013.3\AC701\source\custom_ip\drp_bridge_ip\package\xgui\drp_bridge_v1_0.tcl (3277, 2013-06-27)
2013.3\AC701\source\custom_ip\drp_bridge_ip\rtl (0, 2013-12-11)
2013.3\AC701\source\custom_ip\drp_bridge_ip\rtl\drp_bridge.v (8482, 2013-12-16)
2013.3\AC701\source\custom_ip\drp_mux_ip (0, 2013-12-11)
2013.3\AC701\source\custom_ip\drp_mux_ip\package (0, 2013-12-11)
2013.3\AC701\source\custom_ip\drp_mux_ip\package\component.xml (24911, 2013-10-02)
2013.3\AC701\source\custom_ip\drp_mux_ip\package\drp_mux_0 (0, 2013-12-11)
2013.3\AC701\source\custom_ip\drp_mux_ip\package\drp_mux_0\drp_mux_0.xci (2416, 2013-06-27)
2013.3\AC701\source\custom_ip\drp_mux_ip\package\drp_mux_0\drp_mux_0.xml (19358, 2013-06-27)
2013.3\AC701\source\custom_ip\drp_mux_ip\package\xgui (0, 2013-12-11)
2013.3\AC701\source\custom_ip\drp_mux_ip\package\xgui\drp_mux_v1_0.tcl (253, 2013-06-27)
2013.3\AC701\source\custom_ip\drp_mux_ip\rtl (0, 2013-12-11)
2013.3\AC701\source\custom_ip\drp_mux_ip\rtl\drp_mux.v (6756, 2013-06-22)
2013.3\AC701\source\ipi_tcl (0, 2013-12-11)
2013.3\AC701\source\ipi_tcl\ac701_ipi.tcl (23688, 2013-12-16)
2013.3\AC701\source\rtl (0, 2013-12-11)
2013.3\AC701\source\rtl\EP_MEM.v (69350, 2013-09-22)
2013.3\AC701\source\rtl\pcie_7x_0_pipe_clock.v (21811, 2013-09-22)
... ...

************************************************************************* ____ ____ / /\/ / /___/ \ / \ \ \/ Copyright 2012–2013 Xilinx, Inc. All rights reserved. \ \ This file contains confidential and proprietary / / information of Xilinx, Inc. and is protected under U.S. /___/ /\ and international copyright and other intellectual \ \ / \ property laws. \___\/\___\ ************************************************************************* Vendor: Xilinx Current readme.txt Version: 1.0 Date Last Modified: 18DEC2013 Date Created: 18DEC2013 Associated Filename: xapp11***.zip Associated Document: xapp11***, Incorporating Eye Scan with Supported Device(s): AC701, KC705, VC709, ZC706 ************************************************************************* Disclaimer: This disclaimer is not a license and does not grant any rights to the materials distributed herewith. Except as otherwise provided in a valid license issued to you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under or in connection with these materials, including for any direct, or any indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Critical Applications: Xilinx products are not designed or intended to be fail-safe, or for use in any application requiring fail-safe performance, such as life-support or safety devices or systems, Class III medical devices, nuclear facilities, applications related to the deployment of airbags, or any other applications that could lead to death, personal injury, or severe property or environmental damage (individually and collectively, "Critical Applications"). Customer assumes the sole risk and liability of any use of Xilinx products in Critical Applications, subject only to applicable laws and regulations governing limitations on product liability. THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. ************************************************************************* This readme file contains these sections: 1. REVISION HISTORY 2. OVERVIEW 3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS 4. DESIGN FILE HIERARCHY 5. INSTALLATION AND OPERATING INSTRUCTIONS 6. SUPPORT 1. REVISION HISTORY Readme Date Version Revision Description ========================================================================= 18DEC2013 1.0 Initial Xilinx release. ========================================================================= 2. OVERVIEW This readme describes how to use the files that come with application note (XAPP11***) This Application note describes how to integrate in-syste Eye Scan into an AXI system. This application note leverages the following plug-and-play AXI-based peripherals: MicroBlaze AXI Interconnect Block Memory Controller JTAG to AXI AXI bridge to AXI 3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS The reference design was validated with the following software: * Vivado 2013.3, SDK 2013.3 OR * Vivado 2013.4, SDK 2013.4 * MicroBlaze v9.2 * JTAG to AXI Master v1.0 4. DESIGN FILE HIERARCHY The directory structure underneath this top-level folder is described below: \AC701 or KC705 or VC709 or ZC706 | This folder contains all source files and build stripts | +---- \source | All source files | | +-- \constraints | Constraints for PCI Express IP | | +-- \core | XCI source file for PCI Express IP | | +-- \custom_ip | AXI to DRP bridge is packaged here | | +-- \ipi_tcl | Contains TCL file for building design in IPI | | +-- \rtl | Contains RTL for PCI Express example design | | +-- \software | Directory containing relevant software files | | +--\prebuilt_elf | Contains compiled MicroBlaze software for reference design | +----- \run_here | Contains build scripts | +----- \scan_time | Contains TCL files for running an eye scan | \prebuilt bitstream | | This folder contains prebuilt bitstream for the AC701, KC705 or VC709 | This also contains an image for the ZC706 | These bitstreams have been tested as functioning bitstreams 5. INSTALLATION AND OPERATING INSTRUCTIONS 1) Install the Vivado 2013.3 or 2013.4 2) Make use of either the AC701, KC705, VC709, or the ZC706 directories 3) Plug the evaluation board into a PCI Express Slot 4) Turn on power to Evaluation board then program FPGA 5) Turn on power for Host PC 6) Use provided scripts to perform an eyescan (refer to XAPP for details) 6. SUPPORT To obtain technical support for this reference design, go to www.xilinx.com/support to locate answers to known issues in the Xilinx Answers Database or to create a WebCase.

近期下载者：

相关文件：

评论：[我要评论] [举报此文件]

收藏者：