HSMB
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：8735KB
下载次数：80
上传日期：2015-04-09 22:52:16
上 传 者：
henrykarry
说明： 基于Altera平台的SFP+光模块硬件代码
(Based on Altera Platform, provided a 10G Optic XAUI to SFP+ controller)
文件列表:
assignment_defaults.qdf (52360, 2012-06-05)
CHIP.done (26, 2012-06-05)
CHIP.fit.smsg (499, 2012-06-05)
CHIP.fit.summary (863, 2012-06-05)
CHIP.jdi (21419, 2012-06-05)
CHIP.map.smsg (3050, 2012-06-05)
CHIP.map.summary (640, 2012-06-05)
CHIP.pin (175465, 2012-06-05)
CHIP.qarlog (222, 2012-06-05)
CHIP.qip (576, 2012-06-05)
CHIP.qpf (1241, 2012-06-05)
CHIP.qsf (11787, 2012-06-05)
CHIP.sdc (1169, 2012-06-05)
CHIP.sof (11114554, 2012-06-05)
CHIP.sta.summary (6901, 2012-06-05)
CHIP.ttf (17221869, 2012-06-05)
CHIP.v (11354, 2012-06-05)
CHIP_assignment_defaults.qdf (48264, 2012-06-05)
DEMO (0, 2012-06-05)
DEMO\basic.tcl (1000, 2012-06-05)
DEMO\bcm_phy.tcl (6940, 2012-06-05)
DEMO\demo.tcl (5207, 2012-06-05)
DEMO\eth_inc.tcl (29308, 2012-06-05)
DEMO\gen_inc.tcl (5391, 2012-06-05)
DEMO\mon_inc.tcl (5550, 2012-06-05)
DEMO\regress.tcl (140, 2012-06-05)
DEMO\reg_map.tcl (1568, 2012-06-05)
ETH10G_TOP (0, 2012-06-05)
ETH10G_TOP\synthesis (0, 2012-06-05)
ETH10G_TOP\synthesis\ETH10G.qip (21555, 2012-06-05)
ETH10G_TOP\synthesis\ETH10G.v (9266, 2012-06-05)
ETH10G_TOP\synthesis\submodules (0, 2012-06-05)
ETH10G_TOP\synthesis\submodules\altera_avalon_dc_fifo.sdc (753, 2012-06-05)
ETH10G_TOP\synthesis\submodules\altera_avalon_dc_fifo.v (22841, 2012-06-05)
ETH10G_TOP\synthesis\submodules\altera_avalon_mm_bridge.v (11243, 2012-06-05)
ETH10G_TOP\synthesis\submodules\altera_avalon_sc_fifo.v (31321, 2012-06-05)
ETH10G_TOP\synthesis\submodules\altera_avalon_st_clock_crosser.v (4765, 2012-06-05)
ETH10G_TOP\synthesis\submodules\altera_avalon_st_delay.sv (5455, 2012-06-05)
ETH10G_TOP\synthesis\submodules\altera_avalon_st_handshake_clock_crosser.v (7281, 2012-06-05)
ETH10G_TOP\synthesis\submodules\altera_avalon_st_pipeline_base.v (4580, 2012-06-05)
... ...
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