文件列表:

kc705_pcie\coregen.cgc (112948, 2012-12-11)
kc705_pcie\coregen.cgp (521, 2012-07-17)
kc705_pcie\kc705_pcie_x8_gen2.gise (1187, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2.veo (17694, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2.xco (7835, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2.xise (35333, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\example_design\EP_MEM.v (66444, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\example_design\PIO.v (6108, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\example_design\PIO_EP.v (8634, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\example_design\PIO_EP_MEM_ACCESS.v (11969, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\example_design\PIO_RX_ENGINE.v (44328, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\example_design\PIO_TO_CTRL.v (3734, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\example_design\PIO_TX_ENGINE.v (15132, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\example_design\pcie_app_7x.v (15253, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\example_design\xilinx_pcie_2_1_ep_7x.v (36490, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\example_design\xilinx_pcie_2_1_ep_7x_08_lane_gen2_xc7k325t-ffg900-2_KC705_REVC.ucf (11495, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\example_design\xilinx_pcie_2_1_ep_7x_08_lane_gen2_xc7k325t-ffg900-2_KC705_REVC.xdc (11077, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\hierarchy.txt (2365, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\implement\implement.bat (1224, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\implement\implement.log (820588, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\implement\implement.sh (1313, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\implement\planAhead_rdn.bat (353, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\implement\planAhead_rdn.sh (325, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\implement\planAhead_rdn.tcl (3770, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\implement\results\mapped.mrp (184684, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\implement\results\routed.bit (2801308, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\implement\results\routed.ncd (1974285, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\implement\results\routed.pad (37313, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\implement\results\routed.par (18638, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\implement\xilinx_pcie_2_1_ep_7x.log (720163, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\implement\xilinx_pcie_2_1_ep_7x.ngc (2897302, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\implement\xilinx_pcie_2_1_ep_7x.ngc_xst.xrpt (16247, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\implement\xilinx_pcie_2_1_ep_7x.ngr (4280375, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\implement\xilinx_pcie_2_1_ep_7x.prj (2252, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\implement\xilinx_pcie_2_1_ep_7x.xcf (478, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\implement\xilinx_pcie_2_1_ep_7x.xst (294, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\implement\xst.srp (720163, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\source\kc705_pcie_x8_gen2.v (98217, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\source\kc705_pcie_x8_gen2_axi_basic_rx.v (8493, 2012-12-11)
kc705_pcie\kc705_pcie_x8_gen2\source\kc705_pcie_x8_gen2_axi_basic_rx_null_gen.v (15925, 2012-12-11)
... ...

******************************************************************************* ** Copyright 2012 Xilinx, Inc. All rights reserved. ** This file contains confidential and proprietary information of Xilinx, Inc. and ** is protected under U.S. and international copyright and other intellectual property laws. ******************************************************************************* ** ____ ____ ** / /\/ / ** /___/ \ / Vendor: Xilinx ** \ \ \/ ** \ \ readme.txt ** / / ** /___/ /\ ** \ \ / \ Associated Filename: rdf0106.zip ** \___\/\___\ ** ** Device: Kintex-7 FPGA ** Purpose: PCIe x8 Gen 2 application for the KC705 evaluation board. ** Reference: xtp106.pdf ** ** ******************************************************************************* ** ** Disclaimer: ** ** This disclaimer is not a license and does not grant any rights to the materials ** distributed herewith. Except as otherwise provided in a valid license issued to you ** by Xilinx, and to the maximum extent permitted by applicable law: ** (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, ** AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, ** INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR ** FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract ** or tort, including negligence, or under any other theory of liability) for any loss or damage ** of any kind or nature related to, arising under or in connection with these materials, ** including for any direct, or any indirect, special, incidental, or consequential loss ** or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered ** as a result of any action brought by a third party) even if such damage or loss was ** reasonably foreseeable or Xilinx had been advised of the possibility of the same. ** Critical Applications: ** ** Xilinx products are not designed or intended to be fail-safe, or for use in any application ** requiring fail-safe performance, such as life-support or safety devices or systems, ** Class III medical devices, nuclear facilities, applications related to the deployment of airbags, ** or any other applications that could lead to death, personal injury, or severe property or ** environmental damage (individually and collectively, "Critical Applications"). Customer assumes ** the sole risk and liability of any use of Xilinx products in Critical Applications, subject only ** to applicable laws and regulations governing limitations on product liability. ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. ******************************************************************************* ** IMPORTANT NOTES ** The KC705 PCIe x8 Gen2 application step-by-step instructions are described in xtp106.pdf

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