plj.FPGA
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：9059KB
下载次数：3
上传日期：2015-06-13 23:25:01
上 传 者：
hustliu123
说明： 本频率计基于CPLD/FPGA实现。 50MHZ标准频率为CPLD内部时钟信号，被测方波为信号发生器产生的方波信号，显示电路由TTL芯片及七段数码管组成的电路，自校正输出由CPLD输出已知频率的测试方波信号，可将其输入至测试端口，进行系统精度校正。
(The frequency meter based on CPLD/FPGA implementation. 50MHZ standard CPLD internal clock signal frequency, square-wave test signal is a square wave signal generator, the display circuit circuit TTL chip and composed of seven segments, self-correction output the CPLD output a known frequency square wave test signals can be input to the test port for system accuracy correction.)
文件列表:
plj上FPGA板终结版 (0, 2015-06-01)
plj上FPGA板终结版\.Xil-PlanAhead-1260-WIN7U-20130804N (0, 2015-06-01)
plj上FPGA板终结版\.Xil-PlanAhead-1260-WIN7U-20130804N\ngc2edif (0, 2015-06-01)
plj上FPGA板终结版\.Xil-PlanAhead-1260-WIN7U-20130804N\ngc2edif\ngc2edif.log (385, 2014-03-16)
plj上FPGA板终结版\.Xil-PlanAhead-1260-WIN7U-20130804N\ngc2edif\plj.edif (434639, 2014-03-16)
plj上FPGA板终结版\.Xil-PlanAhead-1260-WIN7U-20130804N\ngc2edif\_xmsgs (0, 2015-06-01)
plj上FPGA板终结版\.Xil-PlanAhead-1260-WIN7U-20130804N\ngc2edif\_xmsgs\ngc2edif.xmsgs (515, 2014-03-16)
plj上FPGA板终结版\.Xil-PlanAhead-6748-WIN7U-20130804N (0, 2015-06-01)
plj上FPGA板终结版\.Xil-PlanAhead-6748-WIN7U-20130804N\ngc2edif (0, 2015-06-01)
plj上FPGA板终结版\.Xil-PlanAhead-6748-WIN7U-20130804N\ngc2edif\ngc2edif.log (385, 2014-03-15)
plj上FPGA板终结版\.Xil-PlanAhead-6748-WIN7U-20130804N\ngc2edif\plj.edif (434640, 2014-03-15)
plj上FPGA板终结版\.Xil-PlanAhead-6748-WIN7U-20130804N\ngc2edif\_xmsgs (0, 2015-06-01)
plj上FPGA板终结版\.Xil-PlanAhead-6748-WIN7U-20130804N\ngc2edif\_xmsgs\ngc2edif.xmsgs (515, 2014-03-15)
plj上FPGA板终结版\.Xil-PlanAhead-8008-WIN7U-20130804N (0, 2015-06-01)
plj上FPGA板终结版\.Xil-PlanAhead-8008-WIN7U-20130804N\ngc2edif (0, 2015-06-01)
plj上FPGA板终结版\.Xil-PlanAhead-8008-WIN7U-20130804N\ngc2edif\ngc2edif.log (385, 2014-03-16)
plj上FPGA板终结版\.Xil-PlanAhead-8008-WIN7U-20130804N\ngc2edif\plj.edif (538226, 2014-03-16)
plj上FPGA板终结版\.Xil-PlanAhead-8008-WIN7U-20130804N\ngc2edif\_xmsgs (0, 2015-06-01)
plj上FPGA板终结版\.Xil-PlanAhead-8008-WIN7U-20130804N\ngc2edif\_xmsgs\ngc2edif.xmsgs (515, 2014-03-16)
plj上FPGA板终结版\chuancan.v (880, 2014-03-13)
plj上FPGA板终结版\display.v (1119, 2014-03-17)
plj上FPGA板终结版\fenpinqi1.cmd_log (209, 2014-03-13)
plj上FPGA板终结版\fenpinqi1.tfi (112, 2014-03-13)
plj上FPGA板终结版\fenpinqi1.v (786, 2014-03-19)
plj上FPGA板终结版\fenpinqi1_isim_beh.exe (82432, 2014-03-13)
plj上FPGA板终结版\fenpinqi1_stx_beh.prj (100, 2014-03-13)
plj上FPGA板终结版\fenpinqi2.v (785, 2014-03-19)
plj上FPGA板终结版\fenpinqi2_isim_beh.exe (82432, 2014-03-13)
plj上FPGA板终结版\fenpinqi2_stx_beh.prj (100, 2014-03-13)
plj上FPGA板终结版\fenpinqi3.v (791, 2014-03-16)
plj上FPGA板终结版\fenpinqi4.v (767, 2014-03-16)
plj上FPGA板终结版\Freq_div1.v (539, 2014-03-13)
plj上FPGA板终结版\fuse.log (2106, 2014-03-20)
plj上FPGA板终结版\fuse.xmsgs (561, 2014-03-20)
plj上FPGA板终结版\fuseRelaunch.cmd (214, 2014-03-20)
plj上FPGA板终结版\gg.wcfg (3182, 2014-03-13)
plj上FPGA板终结版\ipcore_dir (0, 2014-03-09)
plj上FPGA板终结版\iseconfig (0, 2015-06-01)
plj上FPGA板终结版\iseconfig\plj.projectmgr (8402, 2014-03-20)
plj上FPGA板终结版\iseconfig\plj.xreport (20338, 2014-03-26)
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