Verilog
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：12364KB
下载次数：7
上传日期：2015-06-15 23:01:21
上 传 者：
3424493
说明： FPGA开发板资料Verilog，53个例程
(fpga Development board materia)
文件列表:
Verilog (0, 2013-07-10)
Verilog\Verilog程序 (0, 2013-07-10)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示 (0, 2013-07-10)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db (0, 2013-07-10)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.(0).cnf.cdb (2697, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.(0).cnf.hdb (1103, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.asm.qmsg (2451, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.asm_labs.ddb (3342, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.cbx.xml (89, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.cmp.cdb (5493, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.cmp.hdb (7706, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.cmp.kpt (338, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.cmp.logdb (4, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.cmp.rdb (16319, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.cmp.tdb (3923, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.cmp0.ddb (53538, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.cmp2.ddb (41414, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.db_info (151, 2009-12-19)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.eco.cdb (175, 2011-02-10)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.fit.qmsg (21791, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.hier_info (1278, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.hif (759, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.lpc.html (430, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.lpc.rdb (399, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.lpc.txt (1060, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.map.cdb (2049, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.map.hdb (7411, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.map.logdb (4, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.map.qmsg (3952, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.pre_map.cdb (2367, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.pre_map.hdb (7643, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.rtlv.hdb (7627, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.rtlv_sg.cdb (2267, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.rtlv_sg_swap.cdb (192, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.sgdiff.cdb (1828, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.sgdiff.hdb (7667, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.sld_design_entry.sci (168, 2011-02-10)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.sld_design_entry_dsc.sci (168, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.syn_hier_info (0, 2011-02-01)
Verilog\Verilog程序\10实验十：利用语言实现按键和数码管显示\db\key_led.tan.qmsg (36738, 2011-02-01)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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