USB2.0
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：4604KB
下载次数：15
上传日期：2015-06-25 17:02:08
上 传 者：
herakles
说明： usb2.0+FPGA+SDRAM一整套测试程序
(
usb2.0+ FPGA+ SDRAM set of test procedures)
文件列表:
4、test_FPGA_SDRAM_USB2.0 (0, 2015-06-02)
4、test_FPGA_SDRAM_USB2.0\FPGA (0, 2015-06-02)
4、test_FPGA_SDRAM_USB2.0\FPGA\ADC_Controller.vhd (844, 2013-06-24)
4、test_FPGA_SDRAM_USB2.0\FPGA\CLKGen.vhd (716, 2013-03-18)
4、test_FPGA_SDRAM_USB2.0\FPGA\Controller.vhd (2647, 2013-06-25)
4、test_FPGA_SDRAM_USB2.0\FPGA\Controller.vhd.bak (2605, 2013-06-24)
4、test_FPGA_SDRAM_USB2.0\FPGA\FIFO_8Bit_2K.vhd (1286, 2013-06-24)
4、test_FPGA_SDRAM_USB2.0\FPGA\FIFO_Core.cmp (1207, 2013-06-24)
4、test_FPGA_SDRAM_USB2.0\FPGA\FIFO_Core.qip (277, 2013-06-24)
4、test_FPGA_SDRAM_USB2.0\FPGA\FIFO_Core.vhd (8180, 2013-06-24)
4、test_FPGA_SDRAM_USB2.0\FPGA\FIFO_Core_wave0.jpg (140046, 2013-03-10)
4、test_FPGA_SDRAM_USB2.0\FPGA\FIFO_Core_wave1.jpg (136068, 2013-03-10)
4、test_FPGA_SDRAM_USB2.0\FPGA\FIFO_Core_waveforms.html (1115, 2013-03-10)
4、test_FPGA_SDRAM_USB2.0\FPGA\PLL_Core.bsf (4379, 2013-03-18)
4、test_FPGA_SDRAM_USB2.0\FPGA\PLL_Core.cmp (1022, 2013-03-18)
4、test_FPGA_SDRAM_USB2.0\FPGA\PLL_Core.ppf (617, 2013-03-18)
4、test_FPGA_SDRAM_USB2.0\FPGA\PLL_Core.qip (450, 2013-03-18)
4、test_FPGA_SDRAM_USB2.0\FPGA\PLL_Core.vhd (18854, 2013-03-18)
4、test_FPGA_SDRAM_USB2.0\FPGA\SDRAM_Controller.vhd (14064, 2013-06-24)
4、test_FPGA_SDRAM_USB2.0\FPGA\USB2_SDRAM_Project.asm.rpt (8255, 2013-06-25)
4、test_FPGA_SDRAM_USB2.0\FPGA\USB2_SDRAM_Project.cdf (335, 2013-03-20)
4、test_FPGA_SDRAM_USB2.0\FPGA\USB2_SDRAM_Project.done (26, 2013-06-25)
4、test_FPGA_SDRAM_USB2.0\FPGA\USB2_SDRAM_Project.fit.rpt (343609, 2013-06-25)
4、test_FPGA_SDRAM_USB2.0\FPGA\USB2_SDRAM_Project.fit.smsg (513, 2013-06-25)
4、test_FPGA_SDRAM_USB2.0\FPGA\USB2_SDRAM_Project.fit.summary (635, 2013-06-25)
4、test_FPGA_SDRAM_USB2.0\FPGA\USB2_SDRAM_Project.flow.rpt (10996, 2013-06-25)
4、test_FPGA_SDRAM_USB2.0\FPGA\USB2_SDRAM_Project.jdi (21, 2013-06-25)
4、test_FPGA_SDRAM_USB2.0\FPGA\USB2_SDRAM_Project.map.rpt (175860, 2013-06-25)
4、test_FPGA_SDRAM_USB2.0\FPGA\USB2_SDRAM_Project.map.summary (493, 2013-06-25)
4、test_FPGA_SDRAM_USB2.0\FPGA\USB2_SDRAM_Project.merge.rpt (26828, 2013-03-14)
4、test_FPGA_SDRAM_USB2.0\FPGA\USB2_SDRAM_Project.pin (27116, 2013-06-25)
4、test_FPGA_SDRAM_USB2.0\FPGA\USB2_SDRAM_Project.pof (524490, 2013-06-25)
4、test_FPGA_SDRAM_USB2.0\FPGA\USB2_SDRAM_Project.qpf (1274, 2013-03-04)
4、test_FPGA_SDRAM_USB2.0\FPGA\USB2_SDRAM_Project.qsf (7729, 2013-06-25)
4、test_FPGA_SDRAM_USB2.0\FPGA\USB2_SDRAM_Project.qws (1824, 2013-03-20)
4、test_FPGA_SDRAM_USB2.0\FPGA\USB2_SDRAM_Project.sof (151066, 2013-06-25)
4、test_FPGA_SDRAM_USB2.0\FPGA\USB2_SDRAM_Project.sta.rpt (891840, 2013-06-25)
4、test_FPGA_SDRAM_USB2.0\FPGA\USB2_SDRAM_Project.sta.summary (2939, 2013-06-25)
4、test_FPGA_SDRAM_USB2.0\FPGA\USB2_SDRAM_Project.tan.rpt (806577, 2013-03-20)
4、test_FPGA_SDRAM_USB2.0\FPGA\USB2_SDRAM_Project.tan.summary (4612, 2013-03-20)
... ...
This directory contains 8051 firmware for the Cypress Semiconductor EZ-USB FX2
chip.
The purpose of this code is to demonstrate how to utilize EZUSB FX2 Slave Sync Mode
(in a back to back application - FX2 in SLAVE FIFO Sync).
The code is written in C and uses both the EZ-USB FX library and the FrameWorks.
It configures FX2 as follows:
01). EP2 512 4x BULK OUT - 16-bit sync AUTO mode
02). EP6 512 4x BULK IN - 16-bit sync AUTO mode
.....from the slave (in this case is FX2 in Slave FIFO mode)
01). 512 byte buffer for EP2 OUT (master) -> EP6 IN data (slave)
02). 512 byte buffer for EP6 IN (master) -> EP2 OUT data (slave)
04). peripheral interface functions in 16-bit sync mode
.....from "the user":
01). EP2 512 4x BULK OUT data is sent to EP6 512 4x BULK IN
02). EP6 512 4x BULK IN data is received from EP2 512 4x BULK OUT
NOTE: we'll initially test using 16-bit mode so the host application/driver
doesn't need to pad odd data sizes, say 8191 bytes... etc.
The "slave_sync.hex" file loads into internal memory.
...issue "build -i" at the command prompt...
This example is for illustrative purpose(s) and unless you have an ext. slave
that emulates the testing environment this example won't actually produce
expected results when downloaded via Control Panel. The external slave in this
case is EZUSB FX2 running in Slave FIFO mode
In this implementation the master to slave pin assignments are as follows:
slave(FX Slave FIFO SYNC mode) master(FX GPIF SYNC mode)
==================== =========================
SLRD <---- CTL0
SLWR <---- CTL1
SLOE <---- CTL2
FIFOADR0 <---- PA6
FIFOADR1 <---- PA7
FLAGA_PF ----> PA4
FLAGB_FF ----> RDY1
FLAGC_EF ----> RDY0
PA0 ----> INT0#
IFCLK <---> IFCLK
The Control Panel Application may be used to drive this example as described in
the tutorials.
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