proj1
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：63KB
下载次数：1
上传日期：2015-07-02 18:02:58
上 传 者：
srina
说明： EDK project folder for developing simpel appliations
文件列表:
proj1\clock_generator_0.log (418, 2015-06-13)
proj1\data\system.ucf (7260, 2015-06-13)
proj1\etc\bitgen.ut (221, 2015-06-13)
proj1\etc\download.cmd (115, 2015-06-13)
proj1\etc\fast_runtime.opt (2794, 2015-06-13)
proj1\etc\system.filters (9528, 2015-06-13)
proj1\etc\system.gui (12438, 2015-06-13)
proj1\implementation\system_summary.html (3397, 2015-06-13)
proj1\system.bsb (1402, 2015-06-13)
proj1\system.log (175, 2015-06-13)
proj1\system.make (8000, 2015-06-13)
proj1\system.mhs (8237, 2015-06-13)
proj1\system.xmp (537, 2015-06-13)
proj1\system_incl.make (3546, 2015-06-13)
proj1\__xps\bitinit.opt (60, 2015-06-13)
proj1\__xps\edw2xtl_sav_globals.xsl (13184, 2013-10-14)
proj1\__xps\edw2xtl_sav_view.xsl (9158, 2013-10-14)
proj1\__xps\edw2xtl_sav_view_addr.xsl (59429, 2013-10-14)
proj1\__xps\edw2xtl_sav_view_busif.xsl (29787, 2013-10-14)
proj1\__xps\edw2xtl_sav_view_groups.xsl (73114, 2013-10-14)
proj1\__xps\edw2xtl_sav_view_port.xsl (44659, 2013-10-14)
proj1\__xps\gensav_cmd.xml (34, 2015-06-13)
proj1\__xps\ise\system.xreport (21396, 2015-06-13)
proj1\__xps\ise\xmsgprops.lst (96, 2015-06-13)
proj1\__xps\platgen.opt (113, 2015-06-13)
proj1\__xps\simgen.opt (132, 2015-06-13)
proj1\__xps\system.xml (281264, 2015-06-13)
proj1\__xps\xplorer.opt (49, 2015-06-13)
proj1\__xps\xpsxflow.opt (47, 2015-06-13)
proj1\__xps\ise\_xmsgs (0, 2015-06-13)
proj1\__xps\ise (0, 2015-06-13)
proj1\data (0, 2015-06-13)
proj1\etc (0, 2015-06-13)
proj1\implementation (0, 2015-06-13)
proj1\pcores (0, 2015-06-13)
proj1\__xps (0, 2015-06-13)
proj1 (0, 2015-06-13)
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