3.MR_wo_FPGA_DDS_FSK
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：424KB
下载次数：8
上传日期：2015-07-23 22:00:15
上 传 者：
APP117
说明： AD9852 DDS 1MHZ~40MHZ fsk扫频控制代码
(AD9852 DDS 1MHZ~40MHZ controler)
文件列表:
3.MR_wo_FPGA_DDS_FSK\db\logic_util_heursitic.dat (6512, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\prev_cmp_WOFPGAFSK.qmsg (8657, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.(0).cnf.cdb (9893, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.(0).cnf.hdb (1999, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.ace_cmp.bpm (724, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.ace_cmp.cdb (29395, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.ace_cmp.hdb (14022, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.asm.qmsg (2307, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.asm.rdb (1515, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.cbx.xml (91, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.cmp.bpm (724, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.cmp.cdb (29395, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.cmp.hdb (14022, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.cmp.idb (9505, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.cmp.kpt (223, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.cmp.logdb (4, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.cmp.rdb (15491, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.cmp0.ddb (39572, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.cmp_merge.kpt (227, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.db_info (155, 2015-07-22)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.eco.cdb (179, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.fit.qmsg (14922, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.hier_info (1699, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.hif (400, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.ipinfo (178, 2015-07-22)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.lpc.html (372, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.lpc.rdb (414, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.lpc.txt (1060, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.map.ammdb (138, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.map.bpm (690, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.map.cdb (9760, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.map.hdb (12930, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.map.kpt (1370, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.map.logdb (4, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.map.qmsg (5327, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.map.rdb (1255, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.map_bb.cdb (1878, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.map_bb.hdb (9132, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.map_bb.logdb (4, 2015-07-19)
3.MR_wo_FPGA_DDS_FSK\db\WOFPGAFSK.pplq.rdb (247, 2015-07-22)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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